FreeCalypso > hg > freecalypso-schem2

changeset 40:9309cebe07b8

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use buffer_slot_od primitive for slots of 74LVC2G07
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 26 Nov 2021 23:18:12 +0000
parents 3becdb3b6dce
children df16d0eabf8a
files venus/src/primitives venus/src/usb/usb_domain_bctl.v
diffstat 2 files changed, 3 insertions(+), 2 deletions(-) [+]
line wrap: on
line diff
--- a/venus/src/primitives	Fri Nov 26 23:08:09 2021 +0000
+++ b/venus/src/primitives	Fri Nov 26 23:18:12 2021 +0000
@@ -36,6 +36,7 @@
 
 /* logic IC subpackages */
 buffer_slot_basic	mapped_pins (A, Y);
+buffer_slot_od		mapped_pins (A, Y);
 buffer_slot_3state	mapped_pins (A, nOE, Y);
 logic_ic_common		mapped_pins (Vcc, GND);
 x541_common		mapped_pins (Vcc, GND, nOE1, nOE2);
--- a/venus/src/usb/usb_domain_bctl.v	Fri Nov 26 23:08:09 2021 +0000
+++ b/venus/src/usb/usb_domain_bctl.v	Fri Nov 26 23:18:12 2021 +0000
@@ -21,7 +21,7 @@
 
 capacitor od_buf_bypass_cap (P_3V3, GND);
 
-buffer_slot_basic buf_CTL1 (.A(ChanB_RTS), .Y(CTL1_out));
-buffer_slot_basic buf_CTL2 (.A(ChanB_DTR), .Y(CTL2_out));
+buffer_slot_od buf_CTL1 (.A(ChanB_RTS), .Y(CTL1_out));
+buffer_slot_od buf_CTL2 (.A(ChanB_DTR), .Y(CTL2_out));
 
 endmodule