# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1637968692 0
# Node ID 9309cebe07b86f2a6d5364c9b4f8afa55f6af7cc
# Parent  3becdb3b6dce9916d4c46c43bfeb3530a7cddc92
use buffer_slot_od primitive for slots of 74LVC2G07

diff -r 3becdb3b6dce -r 9309cebe07b8 venus/src/primitives
--- a/venus/src/primitives	Fri Nov 26 23:08:09 2021 +0000
+++ b/venus/src/primitives	Fri Nov 26 23:18:12 2021 +0000
@@ -36,6 +36,7 @@
 
 /* logic IC subpackages */
 buffer_slot_basic	mapped_pins (A, Y);
+buffer_slot_od		mapped_pins (A, Y);
 buffer_slot_3state	mapped_pins (A, nOE, Y);
 logic_ic_common		mapped_pins (Vcc, GND);
 x541_common		mapped_pins (Vcc, GND, nOE1, nOE2);
diff -r 3becdb3b6dce -r 9309cebe07b8 venus/src/usb/usb_domain_bctl.v
--- a/venus/src/usb/usb_domain_bctl.v	Fri Nov 26 23:08:09 2021 +0000
+++ b/venus/src/usb/usb_domain_bctl.v	Fri Nov 26 23:18:12 2021 +0000
@@ -21,7 +21,7 @@
 
 capacitor od_buf_bypass_cap (P_3V3, GND);
 
-buffer_slot_basic buf_CTL1 (.A(ChanB_RTS), .Y(CTL1_out));
-buffer_slot_basic buf_CTL2 (.A(ChanB_DTR), .Y(CTL2_out));
+buffer_slot_od buf_CTL1 (.A(ChanB_RTS), .Y(CTL1_out));
+buffer_slot_od buf_CTL2 (.A(ChanB_DTR), .Y(CTL2_out));
 
 endmodule