FreeCalypso > hg > fc-small-hw

view lunalcd2/src/vsrc/bl_current_sink.v @ 59:d5d14b426faa

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents
children
line wrap: on
line source

module bl_current_sink (GND, Vio, BL_EN, LEDK);

input GND, Vio, BL_EN;
output [1:3] LEDK;

wire SET;

MAX1916 MAX1916 (.GND(GND),
		 .EN(BL_EN),
		 .SET(SET),
		 .LEDK(LEDK)
	);

current_select cursel ( .Vio(Vio),
			.SET(SET)
	);

endmodule