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comparison lunalcd2/src/vsrc/bl_current_sink.v @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
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58:99328e0ff61a 59:d5d14b426faa
1 module bl_current_sink (GND, Vio, BL_EN, LEDK);
2
3 input GND, Vio, BL_EN;
4 output [1:3] LEDK;
5
6 wire SET;
7
8 MAX1916 MAX1916 (.GND(GND),
9 .EN(BL_EN),
10 .SET(SET),
11 .LEDK(LEDK)
12 );
13
14 current_select cursel ( .Vio(Vio),
15 .SET(SET)
16 );
17
18 endmodule