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diff lunalcd2/src/vsrc/bl_current_sink.v @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/bl_current_sink.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,18 @@
+module bl_current_sink (GND, Vio, BL_EN, LEDK);
+
+input GND, Vio, BL_EN;
+output [1:3] LEDK;
+
+wire SET;
+
+MAX1916 MAX1916 (.GND(GND),
+		 .EN(BL_EN),
+		 .SET(SET),
+		 .LEDK(LEDK)
+	);
+
+current_select cursel ( .Vio(Vio),
+			.SET(SET)
+	);
+
+endmodule