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annotate lunalcd2/src/vsrc/board.v @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents lunalcd1/src/schem.v@28a0574af823
children
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1 module board ();
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2
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3 wire GND, VBAT, Vio, Vio_LCD;
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4 wire [15:0] DB;
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5 wire RD, WR, RS, CS, RESET;
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6 wire BL_EN;
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7 wire [1:3] LEDK; /* 1=left, 2=middle, 3=right for layout */
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8
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9 /* main interface connector */
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10
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11 header_26pin main_if ( .pin_1(DB[15]),
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12 .pin_2(DB[14]),
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13 .pin_3(DB[13]),
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14 .pin_4(DB[12]),
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15 .pin_5(DB[11]),
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16 .pin_6(DB[10]),
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17 .pin_7(DB[9]),
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18 .pin_8(DB[8]),
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19 .pin_9(DB[7]),
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20 .pin_10(DB[6]),
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21 .pin_11(DB[5]),
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22 .pin_12(DB[4]),
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23 .pin_13(DB[3]),
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24 .pin_14(DB[2]),
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25 .pin_15(DB[1]),
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26 .pin_16(DB[0]),
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27 .pin_17(CS),
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28 .pin_18(RD),
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29 .pin_19(WR),
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30 .pin_20(RS),
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31 .pin_21(GND),
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32 .pin_22(GND),
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33 .pin_23(RESET),
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34 .pin_24(Vio),
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35 .pin_25(BL_EN),
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36 .pin_26(GND)
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37 );
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38
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39 resistor BL_EN_pulldown (BL_EN, GND);
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41 /* backlight power supply */
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43 header_2pin VBAT_conn ( .pin_1(VBAT),
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44 .pin_2(GND)
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45 );
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47 /* LCD module */
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49 resistor LCD_current_meas (Vio, Vio_LCD);
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50
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51 capacitor LCD_bypass_cap (Vio_LCD, GND);
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52
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53 lcd_module lcd (.GND(GND),
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54 .VCI(Vio_LCD),
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55 .IOVCC(Vio_LCD),
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56 .DB(DB),
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57 .RD(RD),
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58 .WR(WR),
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59 .RS(RS),
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60 .CS(CS),
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61 .RESET(RESET),
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62 .IM0(GND),
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63 .LEDA(VBAT),
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64 /* LEDK order for layout */
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65 .LEDK[1](LEDK[3]),
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66 .LEDK[2](LEDK[2]),
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67 .LEDK[3](LEDK[1])
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68 );
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69
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70 /* MAX1916-based backlight LED current sink */
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71
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72 bl_current_sink bl_current_sink (.GND(GND),
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73 .Vio(Vio),
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74 .BL_EN(BL_EN),
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75 .LEDK(LEDK)
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76 );
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77
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78 endmodule