view lunalcd2/src/vsrc/board.v @ 59:d5d14b426faa

lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents lunalcd1/src/schem.v@28a0574af823
children
line wrap: on
line source

module board ();

wire GND, VBAT, Vio, Vio_LCD;
wire [15:0] DB;
wire RD, WR, RS, CS, RESET;
wire BL_EN;
wire [1:3] LEDK;	/* 1=left, 2=middle, 3=right for layout */

/* main interface connector */

header_26pin main_if (  .pin_1(DB[15]),
			.pin_2(DB[14]),
			.pin_3(DB[13]),
			.pin_4(DB[12]),
			.pin_5(DB[11]),
			.pin_6(DB[10]),
			.pin_7(DB[9]),
			.pin_8(DB[8]),
			.pin_9(DB[7]),
			.pin_10(DB[6]),
			.pin_11(DB[5]),
			.pin_12(DB[4]),
			.pin_13(DB[3]),
			.pin_14(DB[2]),
			.pin_15(DB[1]),
			.pin_16(DB[0]),
			.pin_17(CS),
			.pin_18(RD),
			.pin_19(WR),
			.pin_20(RS),
			.pin_21(GND),
			.pin_22(GND),
			.pin_23(RESET),
			.pin_24(Vio),
			.pin_25(BL_EN),
			.pin_26(GND)
	);

resistor BL_EN_pulldown (BL_EN, GND);

/* backlight power supply */

header_2pin VBAT_conn ( .pin_1(VBAT),
			.pin_2(GND)
	);

/* LCD module */

resistor LCD_current_meas (Vio, Vio_LCD);

capacitor LCD_bypass_cap (Vio_LCD, GND);

lcd_module lcd (.GND(GND),
		.VCI(Vio_LCD),
		.IOVCC(Vio_LCD),
		.DB(DB),
		.RD(RD),
		.WR(WR),
		.RS(RS),
		.CS(CS),
		.RESET(RESET),
		.IM0(GND),
		.LEDA(VBAT),
		/* LEDK order for layout */
		.LEDK[1](LEDK[3]),
		.LEDK[2](LEDK[2]),
		.LEDK[3](LEDK[1])
	);

/* MAX1916-based backlight LED current sink */

bl_current_sink bl_current_sink (.GND(GND),
				 .Vio(Vio),
				 .BL_EN(BL_EN),
				 .LEDK(LEDK)
	);

endmodule