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annotate lunalcd2/src/vsrc/bl_current_sink.v @ 83:9efa98ea62e5

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sim-fpc-pasv: PCB layout done
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 25 Oct 2022 07:31:52 +0000
parents d5d14b426faa
children
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1 module bl_current_sink (GND, Vio, BL_EN, LEDK);
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2
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3 input GND, Vio, BL_EN;
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4 output [1:3] LEDK;
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5
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6 wire SET;
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7
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8 MAX1916 MAX1916 (.GND(GND),
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9 .EN(BL_EN),
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10 .SET(SET),
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11 .LEDK(LEDK)
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12 );
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13
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14 current_select cursel ( .Vio(Vio),
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15 .SET(SET)
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16 );
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17
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18 endmodule