FreeCalypso > hg > fc-sim-sniff
changeset 9:10c779b8753e
FPGA Makefile: capture yosys stdout
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Mon, 21 Aug 2023 01:00:16 +0000 |
| parents | 7cab8e0dd937 |
| children | db8acc067542 |
| files | fpga/sniffer-basic/Makefile |
| diffstat | 1 files changed, 1 insertions(+), 1 deletions(-) [+] |
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--- a/fpga/sniffer-basic/Makefile Mon Aug 21 00:55:33 2023 +0000 +++ b/fpga/sniffer-basic/Makefile Mon Aug 21 01:00:16 2023 +0000 @@ -5,7 +5,7 @@ all: ${PROJ}.bin ${PROJ}.json: ${VSRC} - yosys-wrap top $@ ${VSRC} + yosys-wrap top $@ ${VSRC} | tee synthesis.rpt ${PROJ}.asc: ${PROJ}.json ${PCF} nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \