FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-pps/sniff_rx.v @ 48:1068f9fd41d5

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doc: project rename
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 21 Sep 2023 06:31:34 +0000
parents ab37fcb71744
children
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1 /*
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2 * This Verilog module captures the ISO 7816-3 character sniffing receiver.
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3 */
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4
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5 module sniff_rx (IntClk, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
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6 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit,
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7 speed_enh_mode, speed_enh_mult);
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8
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9 input IntClk;
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10 input SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
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11 output Rx_strobe, Rx_error;
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12 output [7:0] Rx_char;
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13 output Rx_start_bit, Rx_parity_bit;
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14 input speed_enh_mode;
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15 input [1:0] speed_enh_mult;
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16
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17 wire SIM_CLK_edge;
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18
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19 clk_edge clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
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20
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21 reg [9:0] etu_0p5, etu_1p0, etu_1p5; /* combinational */
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22
31
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23 always @*
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24 casez ({speed_enh_mode,speed_enh_mult})
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25 3'b0??:
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26 begin
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27 /* F/D = 372 */
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28 etu_0p5 = 10'd185;
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29 etu_1p0 = 10'd371;
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30 etu_1p5 = 10'd557;
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31 end
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32 3'b100:
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33 begin
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34 /* F/D = 64 */
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35 etu_0p5 = 10'd31;
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36 etu_1p0 = 10'd63;
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37 etu_1p5 = 10'd95;
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38 end
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39 3'b101:
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40 begin
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41 /* F/D = 32 */
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42 etu_0p5 = 10'd15;
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43 etu_1p0 = 10'd31;
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44 etu_1p5 = 10'd47;
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45 end
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46 3'b110:
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47 begin
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48 /* F/D = 16 */
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49 etu_0p5 = 10'd7;
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50 etu_1p0 = 10'd15;
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51 etu_1p5 = 10'd23;
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52 end
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53 3'b111:
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54 begin
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55 /* F/D = 8 */
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56 etu_0p5 = 10'd3;
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57 etu_1p0 = 10'd7;
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58 etu_1p5 = 10'd11;
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59 end
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60 endcase
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61
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62 reg rx_active;
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63 reg [9:0] clk_count;
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64 reg [3:0] bit_count;
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65 reg [9:0] shift_reg;
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66
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67 always @(posedge IntClk)
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68 if (!SIM_RST_sync)
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69 rx_active <= 1'b0;
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70 else if (!rx_active && !SIM_IO_sync)
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71 begin
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72 rx_active <= 1'b1;
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73 clk_count <= etu_0p5;
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74 bit_count <= 4'd0;
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75 end
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76 else if (rx_active && SIM_CLK_edge)
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77 begin
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78 if (clk_count != 10'd0)
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79 clk_count <= clk_count - 10'd1;
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80 else begin
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81 shift_reg <= {SIM_IO_sync,shift_reg[9:1]};
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82 bit_count <= bit_count + 4'd1;
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83 if (bit_count == 4'd9)
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84 clk_count <= etu_1p5;
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85 else
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86 clk_count <= etu_1p0;
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87 if (bit_count == 4'd10)
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88 rx_active <= 1'b0;
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89 end
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90 end
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91
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92 assign Rx_strobe = rx_active && SIM_CLK_edge && clk_count == 10'd0 &&
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93 bit_count == 4'd10;
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94 assign Rx_error = Rx_strobe && !SIM_IO_sync;
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95 assign Rx_char = shift_reg[8:1];
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96 assign Rx_start_bit = shift_reg[0];
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97 assign Rx_parity_bit = shift_reg[9];
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98
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99 endmodule