--- a/fpga/sniffer-pps/sniff_rx.v	Tue Aug 29 20:36:34 2023 +0000
+++ b/fpga/sniffer-pps/sniff_rx.v	Tue Aug 29 21:22:37 2023 +0000
@@ -3,24 +3,61 @@
  */
 
 module sniff_rx (IntClk, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
-		 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
+		 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit,
+		 speed_enh_mode, speed_enh_mult);
 
 input IntClk;
 input SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
 output Rx_strobe, Rx_error;
 output [7:0] Rx_char;
 output Rx_start_bit, Rx_parity_bit;
+input speed_enh_mode;
+input [1:0] speed_enh_mult;
 
 wire SIM_CLK_edge;
 
 clk_edge clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
 
-wire [9:0] etu_0p5, etu_1p0, etu_1p5;
+reg [9:0] etu_0p5, etu_1p0, etu_1p5;	/* combinational */
 
-/* Fi/Di=372 only for now */
-assign etu_0p5 = 10'd185;
-assign etu_1p0 = 10'd371;
-assign etu_1p5 = 10'd557;
+always @*
+	casez ({speed_enh_mode,speed_enh_mult})
+		3'b0??:
+		    begin
+			/* F/D = 372 */
+			etu_0p5 = 10'd185;
+			etu_1p0 = 10'd371;
+			etu_1p5 = 10'd557;
+		    end
+		3'b100:
+		    begin
+			/* F/D = 64 */
+			etu_0p5 = 10'd31;
+			etu_1p0 = 10'd63;
+			etu_1p5 = 10'd95;
+		    end
+		3'b101:
+		    begin
+			/* F/D = 32 */
+			etu_0p5 = 10'd15;
+			etu_1p0 = 10'd31;
+			etu_1p5 = 10'd47;
+		    end
+		3'b110:
+		    begin
+			/* F/D = 16 */
+			etu_0p5 = 10'd7;
+			etu_1p0 = 10'd15;
+			etu_1p5 = 10'd23;
+		    end
+		3'b111:
+		    begin
+			/* F/D = 8 */
+			etu_0p5 = 10'd3;
+			etu_1p0 = 10'd7;
+			etu_1p5 = 10'd11;
+		    end
+	endcase
 
 reg rx_active;
 reg [9:0] clk_count;