FreeCalypso > hg > fc-selenite

annotate src/cs/system/bootloader/src/bootloader.s @ 168:aa2956979fcb

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src/cs/system: MEMIF and init updates from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 19 Jun 2019 04:05:38 +0000
parents b6a5e36de839
children
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1 ;/******************************************************************************
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2 ; *
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3 ; * BOOTLOADER.S
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4 ; *
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5 ; * This module initializes the system stack for the bootloader and calls the bootloader.
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6 ; * If the bootloader starts the function INT_Initialize is called.
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7 ; *
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8 ; * (C) Texas Instruments 1999
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9 ; *
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10 ; *****************************************************************************/
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11
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12 ;
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13 ;/* Define constants used in low-level initialization. */
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14 ;
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15
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16 LOCKOUT .equ 00C0h ; Interrupt lockout value
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17 MODE_MASK .equ 001Fh ; Processor Mode Mask
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18 SUP_MODE .equ 0013h ; Supervisor Mode (SVC)
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19
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20 SYSTEM_SIZE .equ 1024 ; Define the system stack size
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21
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22 .ref _sta_select_application
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23 .ref _INT_Initialize
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24
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25 .ref end ; Ending address of BSS section
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26
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27
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28 .sect ".text"
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29
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30 .def _INT_Bootloader_Start
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31
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32
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33
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34 addrCS0 .word 0xfffffb00 ;CS0 address space
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35
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36
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37 .if BOARD = 6 ; EVA4
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38 .if CHIPSET != 12
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39 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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40 CS1_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
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41 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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42 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
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43 CS4_MEM_REG .short 0xe85 ; default reset value
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44 .endif
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45
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46 .if CHIPSET = 3
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47 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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48
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49 .elseif CHIPSET = 4
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50 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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51 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
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52
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53 .elseif CHIPSET = 5
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54 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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55
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56 .elseif CHIPSET = 6
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57 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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58
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59 .elseif CHIPSET = 7
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60 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
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61 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
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62
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63 .elseif CHIPSET = 8
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64 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
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65 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
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66
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67 .elseif CHIPSET = 10
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68 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
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69 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
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70
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71 .elseif CHIPSET = 11
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72 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
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73 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
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74
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75 .elseif CHIPSET = 12
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76 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
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77 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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78 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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79 .endif
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80
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81 .elseif BOARD = 7 ; B-Sample
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82 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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83 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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84 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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85 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
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86 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
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87
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88 .if CHIPSET = 3
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89 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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90
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91 .elseif CHIPSET = 4
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92 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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93 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
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94
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95 .elseif CHIPSET = 5
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96 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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97
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98 .elseif CHIPSET = 6
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99 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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100
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101 .endif
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102
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103 .elseif BOARD = 8 ; C-Sample SRAM CS0
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104 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
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105 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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106 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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107 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
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108 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
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109
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110 .if CHIPSET = 4
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111 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
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112 CS7_MEM_REG .short 0x0c0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
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113
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114 .elseif CHIPSET = 7
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115 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
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116 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
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117
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118 .elseif CHIPSET = 8
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119 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
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120 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
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121 .endif
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122
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123 .elseif BOARD = 9 ; C-Sample FLASH CS0
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124 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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125 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 .if CHIPSET = 4
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 CS7_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 .elseif CHIPSET = 7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 .elseif CHIPSET = 8
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 .endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 .elseif BOARD = 40 ; D-Sample SRAM CS0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 CS1_MEM_REG .short 0x2a3 ; 1 Dummy Cycle 16 bit 3 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 .if CHIPSET = 8
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 .elseif CHIPSET = 10
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 .elseif CHIPSET = 11
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 .endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 .elseif BOARD = 41 ; D-Sample FLASH CS0
168
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
164
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
165 ; FreeCalypso change, please see MEMIF-wait-states document
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
166 ; in the freecalypso-docs repository for the explanation.
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
167
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
168 .if VCXO_26MHZ = 1
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
169 CS0_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
170 CS1_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
171 CS2_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
172 .else
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
168
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
176 .endif
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 .if CHIPSET = 8
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 .elseif CHIPSET = 10
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 .elseif CHIPSET = 11
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 .endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 .elseif BOARD = 43 ; E-Sample - FLASH
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 .if CHIPSET != 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 .else
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE BOARD 43 - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 .endif ; CHIPSET = 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 .elseif BOARD = 45 ; EVA_CONSO - FLASH
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 .if CHIPSET != 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 .else
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE BOARD 43 - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 .endif ; CHIPSET = 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 .endif ; BOARD = 6 or 7 or 8 or 9 or 40 or 41 or 43 or 45
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 CTL_MEM_REG .short 0x02a ; rhea strobe 0/1 + API access size adaptation
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 .if CHIPSET = 4
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 RHEA_CNTL_REG .word 0xFFFFF900 ; RHEA control register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 ; Use DPLL, Divide by 1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 RHEA_CONTROL_RST .short 0xFF22 ; Set access factor in order to access the DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 ; independently of the ARM clock
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 .elseif CHIPSET = 6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 ; Constants to configure ULYSSE G1 with VTCXO at 26MHz
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 CNTLCLK_26MHZ_SELECTOR .short 0x0040 ; VTCXO_26 selector
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 .elseif CHIPSET = 7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 ; Use DPLL, Divide by 1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 .elseif CHIPSET = 8
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 ; Use DPLL, Divide by 1
168
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
265 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 .elseif CHIPSET = 10
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 ; Use DPLL, Divide by 1
168
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
277 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 .elseif CHIPSET = 11
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 ; Use DPLL, Divide by 1
168
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
289 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 .elseif CHIPSET = 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 ; Use DPLL, Divide by 1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 DBG_DMA_P2_RST .short 0x0002 ; DBG_DMA_P2 register reset value - GPO2 replaces ADD24
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 CLKM_MEM_REG .equ 0x31 ;the same define INIT_CLKM_ARM_CLK = 0x1031 for InitArmAfterReset
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 _INT_Bootloader_Start
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 ; Basic initializations
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 ; Configuration of ARM clock and DPLL frequency
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 .if CHIPSET = 4
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 ; Configure RHEA access factor in order to allow the access of DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 ldr r1,RHEA_CNTL_REG ; Load address of RHEA control register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 ldrh r2,RHEA_CONTROL_RST ; Load RHEA configuration value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 strh r2,[r1] ; Store DPLL reset value in RHEA control register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 ; Configure DPLL register with reset value
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 strh r2,[r1] ; Store DPLL reset value in DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 ; Wait that DPLL goes in BYPASS mode
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 Wait_DPLL_Bypass
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 ldr r2,[r1] ; Load DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 and r2,r2,#1 ; Perform a mask on bit 0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 cmp r2,#1 ; Compare DPLL lock bit
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 ; generate ARM clock with division factor of 1.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 .elseif CHIPSET = 6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 ; Setting of VTCXO_26MHZ bit to '1' in order to divide reference clock for peripherals.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 ; This setting is required on ULYSSE G1 with a VTCXO clock to 26MHz.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 ldr r1,CNTL_ARM_CLK_REG ; Load CLKM base register address in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359 ldrh r2,[r1,#2] ; Load contents of CNTL_CLK register in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 ldr r0,CNTLCLK_26MHZ_SELECTOR ; Load configuration of 26MHz selector
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 orr r0,r0,r2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 strh r0,[r1,#2]
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 .elseif CHIPSET = 7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 ; Configure DPLL register with reset value
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 strh r2,[r1] ; Store DPLL reset value in DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 ; Wait that DPLL goes in BYPASS mode
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 Wait_DPLL_Bypass
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 ldr r2,[r1] ; Load DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 and r2,r2,#1 ; Perform a mask on bit 0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 cmp r2,#1 ; Compare DPLL lock bit
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 ; generate ARM clock with division factor of 1.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 ; Disable the DU module by setting bit 11 to '1'
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 ldrh r0,[r1] ; Load Extra Control register CONF in r0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 orr r0,r0,r2 ; Disable DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 strh r0,[r1] ; Store configuration in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 ; Disable all MPU protections
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 strh r2,[r1] ; Store reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 .elseif CHIPSET = 8
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 ; Configure DPLL register with reset value
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 strh r2,[r1] ; Store DPLL reset value in DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 ; Wait that DPLL goes in BYPASS mode
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 Wait_DPLL_Bypass
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 ldr r2,[r1] ; Load DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 and r2,r2,#1 ; Perform a mask on bit 0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 cmp r2,#1 ; Compare DPLL lock bit
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 ; generate ARM clock with division factor of 1.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 ; Disable the DU module by setting bit 11 to '1'
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 ldrh r0,[r1] ; Load Extra Control register CONF in r0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 orr r0,r0,r2 ; Disable DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 strh r0,[r1] ; Store configuration in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 ; Disable all MPU protections
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 strh r2,[r1] ; Store reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 .elseif CHIPSET = 10
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 ; Configure DPLL register with reset value
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 strh r2,[r1] ; Store DPLL reset value in DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 ; Wait that DPLL goes in BYPASS mode
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458 Wait_DPLL_Bypass
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 ldr r2,[r1] ; Load DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 and r2,r2,#1 ; Perform a mask on bit 0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461 cmp r2,#1 ; Compare DPLL lock bit
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 ; generate ARM clock with division factor of 1.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 ; Disable the DU module by setting bit 11 to '1'
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
476 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
477 ldrh r0,[r1] ; Load Extra Control register CONF in r0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478 orr r0,r0,r2 ; Disable DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
479 strh r0,[r1] ; Store configuration in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
481 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482 ; Disable all MPU protections
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
483 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
484 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486 strh r2,[r1] ; Store reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488 .elseif CHIPSET = 11
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
490 ; Configure DPLL register with reset value
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
491 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
493 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494 strh r2,[r1] ; Store DPLL reset value in DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
496 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497 ; Wait that DPLL goes in BYPASS mode
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 Wait_DPLL_Bypass
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500 ldr r2,[r1] ; Load DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 and r2,r2,#1 ; Perform a mask on bit 0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 cmp r2,#1 ; Compare DPLL lock bit
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 ; generate ARM clock with division factor of 1.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 ; Disable the DU module by setting bit 11 to '1'
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
516 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 ldrh r0,[r1] ; Load Extra Control register CONF in r0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519 orr r0,r0,r2 ; Disable DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 strh r0,[r1] ; Store configuration in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523 ; Disable all MPU protections
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
525 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527 strh r2,[r1] ; Store reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
528
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529 .elseif CHIPSET = 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
530 .if BOARD = 6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
531 ; Configure DBG_DMA_P2 reg => GPO_2 output pin for EVA4
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
532 ldr r1,DBG_DMA_P2 ; Load address of DBG_DMA_P2 register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
533 ldrh r2,DBG_DMA_P2_RST ; Load DBG_DMA_P2 reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
534 strh r2,[r1] ; Store reset value in register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
535 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
536 .endif ; BOARD = 6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
537 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
538 ; Configure DPLL register with reset value
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
539 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
540 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
541 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
542 strh r2,[r1] ; Store DPLL reset value in DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
543
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
544 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
545 ; Wait that DPLL goes in BYPASS mode
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
546 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
547 Wait_DPLL_Bypass
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
548 ldr r2,[r1] ; Load DPLL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
549 and r2,r2,#1 ; Perform a mask on bit 0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
550 cmp r2,#1 ; Compare DPLL lock bit
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
551 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
552
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
553 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
554 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
555 ; generate ARM clock with division factor of 1.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
556 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
557 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
558 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
559 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
560
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
561 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
562 ; Disable the DU module by setting bit 11 to '1'
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
563 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
564 ; ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
565 ; ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
566 ; ldrh r0,[r1] ; Load Extra Control register CONF in r0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
567 ; orr r0,r0,r2 ; Disable DU module
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
568 ; strh r0,[r1] ; Store configuration in Extra Control register CONF
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
569
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
570 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
571 ; Disable all MPU protections
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
572 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
573 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
574 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
575 strh r2,[r1] ; Store reset value of MPU_CTL register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
576
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
577 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
578
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
579 ldr r1,addrCS0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
580
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
581 .if CHIPSET = 12
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
582 ldrh r2,CS0_MEM_REG ; CALYPSO PLUS TEST MODE - TO BE ERASED - ROM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
583 strh r2,[r1, #0x00] ; CS5
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
584
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
585 ldrh r2,CS5_MEM_REG ; ROM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
586 strh r2,[r1, #0x0A] ; CS5
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
587
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
588 ldrh r2,CS4_MEM_REG ; RAM Initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
589 strh r2,[r1,#0x08] ; CS4
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
590
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
591 .else
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
592 ldrh r2,CS0_MEM_REG ; ROM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
593 strh r2,[r1] ; CS0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
594
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
595 ldrh r2,CS1_MEM_REG ; RAM Initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
596 strh r2,[r1,#2] ; CS1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
597
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
598 ldrh r2,CS2_MEM_REG ; RAM Initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
599 strh r2,[r1,#4] ; CS2
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
600
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
601 ldrh r2,CS3_MEM_REG ; parallel I/O
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
602 strh r2,[r1,#6] ; CS3
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
603
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
604 ldrh r2,CS4_MEM_REG ; Debug Latch
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
605 strh r2,[r1,#0xa] ; CS4
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
606 .endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
607
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
608 .if CHIPSET = 3
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
609 ldrh r2,CS6_MEM_REG ; Ulysse/G0 Internal SRAM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
610 strh r2,[r1,#0xc] ; CS6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
611
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
612 .elseif CHIPSET = 4
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
613 ldrh r2,CS6_MEM_REG ; Samson Internal SRAM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
614 strh r2,[r1,#0xc] ; CS6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
615
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
616 ldrh r2,CS7_MEM_REG ; Internal Boot RAM
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
617 strh r2,[r1,#0x8] ; CS7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
618
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
619 .elseif CHIPSET = 5
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
620 ldrh r2,CS6_MEM_REG ; Ulysse/G1 Internal SRAM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
621 strh r2,[r1,#0xc] ; CS6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
622
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
623 .elseif CHIPSET = 6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
624 ldrh r2,CS6_MEM_REG ; Ulysse/G1 Internal SRAM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
625 strh r2,[r1,#0xc] ; CS6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
626
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
627 .elseif CHIPSET = 7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
628 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
629 strh r2,[r1,#0xc] ; CS6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
630
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
631 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
632 strh r2,[r1,#0x8] ; CS7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
633
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
634 .elseif CHIPSET = 8
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
635 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
636 strh r2,[r1,#0xc] ; CS6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
637
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
638 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
639 strh r2,[r1,#0x8] ; CS7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
640
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
641 .elseif CHIPSET = 10
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
642 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
643 strh r2,[r1,#0xc] ; CS6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
644
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
645 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
646 strh r2,[r1,#0x8] ; CS7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
647
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
648 .elseif CHIPSET = 11
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
649 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
650 strh r2,[r1,#0xc] ; CS6
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
651
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
652 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
653 strh r2,[r1,#0x8] ; CS7
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
654
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
655 .endif ; CHIPSET = 3 or 4 or 5 or 6 or 7 or 8 or 10 or 11
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
656
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
657 ldrh r2,CTL_MEM_REG ; API-RHEA configuration
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
658 strh r2,[r1,#0xe]
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
659
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
660 ; Initialize the system stack to allow to use the bootloader.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
661
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
662 LDR a1,BSS_End ; Pickup the ending address of BSS
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
663 MOV a2,#SYSTEM_SIZE ; Pickup system stack size
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
664 SUB a2,a2,#4 ; Subtract one word for first addr
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
665 ADD a3,a1,a2 ; Build start of system stack area
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
666 BIC a3,a3,#3 ; Insure word aligment of stack
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
667 MOV sp,a3 ; Setup initial stack pointer
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
668
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
669
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
670 ; Call the function which allows to select the bootloader or the user's
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
671 ; application.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
672
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
673 STMFD sp!, {a1-a4,R12}
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
674 BL _sta_select_application
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
675 LDMFD sp!, {a1-a4,R12}
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
676
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
677 B _INT_Initialize
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
678
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
679 ; /* Define all the global addresses used in this section */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
680
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
681 BSS_End
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
682 .word end
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
683
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
684 .end
168
aa2956979fcb src/cs/system: MEMIF and init updates from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
685