FreeCalypso > hg > fc-selenite

diff src/cs/system/bootloader/src/bootloader.s @ 168:aa2956979fcb

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src/cs/system: MEMIF and init updates from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 19 Jun 2019 04:05:38 +0000
parents b6a5e36de839
children
line wrap: on
line diff
--- a/src/cs/system/bootloader/src/bootloader.s	Wed Jun 19 03:57:35 2019 +0000
+++ b/src/cs/system/bootloader/src/bootloader.s	Wed Jun 19 04:05:38 2019 +0000
@@ -161,9 +161,19 @@
             .endif
 
           .elseif   BOARD = 41       ; D-Sample FLASH CS0
+
+; FreeCalypso change, please see MEMIF-wait-states document
+; in the freecalypso-docs repository for the explanation.
+
+    .if VCXO_26MHZ = 1
+CS0_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+CS1_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+CS2_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+    .else
 CS0_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
 CS1_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
 CS2_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
+    .endif
 CS3_MEM_REG   .short  0x283  ; 1 Dummy Cycle  8 bit 3 WS SW BP enable
 CS4_MEM_REG   .short  0x281  ; 1 Dummy Cycle  8 bit 1 WS SW BP enable
 
@@ -252,7 +262,7 @@
 
 CNTL_ARM_CLK_RST  .short  0x1081	   ; Initialization of CNTL_ARM_CLK register
                                      ; Use DPLL, Divide by 1
-DPLL_CONTROL_RST  .short  0x2006     ; Configure DPLL in default state
+DPLL_CONTROL_RST  .short  0x2002     ; Configure DPLL in BYPASS mode, /1
 DISABLE_DU_MASK   .short  0x0800     ; Mask to Disable the DU module
 MPU_CTL_RST       .short  0x0000     ; Reset value of MPU_CTL register - All protections disabled
 
@@ -264,7 +274,7 @@
 
 CNTL_ARM_CLK_RST  .short  0x1081	   ; Initialization of CNTL_ARM_CLK register
                                      ; Use DPLL, Divide by 1
-DPLL_CONTROL_RST  .short  0x2006     ; Configure DPLL in default state
+DPLL_CONTROL_RST  .short  0x2002     ; Configure DPLL in BYPASS mode, /1
 DISABLE_DU_MASK   .short  0x0800     ; Mask to Disable the DU module
 MPU_CTL_RST       .short  0x0000     ; Reset value of MPU_CTL register - All protections disabled
 
@@ -276,7 +286,7 @@
 
 CNTL_ARM_CLK_RST  .short  0x1081	   ; Initialization of CNTL_ARM_CLK register
                                      ; Use DPLL, Divide by 1
-DPLL_CONTROL_RST  .short  0x2006     ; Configure DPLL in default state
+DPLL_CONTROL_RST  .short  0x2002     ; Configure DPLL in BYPASS mode, /1
 DISABLE_DU_MASK   .short  0x0800     ; Mask to Disable the DU module
 MPU_CTL_RST       .short  0x0000     ; Reset value of MPU_CTL register - All protections disabled
 
@@ -672,4 +682,4 @@
     .word   end
 
         .end
-        
\ No newline at end of file
+