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annotate src/cs/system/main/gcc/bootentry.S @ 90:2de9e5f46550

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.../main/gcc/bootentry.S: the literal pool needs to be arranged the way TI had it
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 20 Jul 2018 23:39:27 +0000
parents b398f288d20a
children 2c82c413775f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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b398f288d20a src/cs/system/main/gcc/bootentry.S: written
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1 /*
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2 * This assembly module is our counterpart to TI's int.s: all boot entry
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3 * point code that needs to be at the beginning of the flash resides here.
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4 */
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5
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6 #include "asm_defs.h"
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7 #include "fc-target.cfg"
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8
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9 #if defined(FLASH) && !defined(CONFIG_TARGET_COMPAL)
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10 /*
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11 * Put something sensible in the boot ROM overlay area, just for the
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12 * heck of it, or for extra robustness.
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13 */
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14 .section bootrom.overlay,"ax",%progbits
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15 .code 32
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16 .org 0
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17 b BootROM_disabled_entry
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18 #include "vectors.S"
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19 BootROM_disabled_entry:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
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20 /* copy the boot ROM switch code to IRAM and jump to it */
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21 ldr r4, =__romswitch_flash_addr
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22 ldr r5, =__romswitch_ram_addr
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23 ldr r2, =__romswitch_size
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24 1: ldr r0, [r4], #4
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25 str r0, [r5], #4
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26 subs r2, r2, #4
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27 bhi 1b
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28 ldr pc, =__romswitch_ram_addr
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29
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30 .section bootrom.switch,"ax",%progbits
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31 .code 32
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32 .org 0
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33 @ enable the Calypso boot ROM
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34 ldr r1, =0xFFFFFB10
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35 mov r2, #0x0100
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36 strh r2, [r1]
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37 @ jump to it!
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38 mov pc, #0
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39 #endif
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40
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41 .section .inttext,"ax",%progbits
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42 .code 32
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43
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44 #ifdef FLASH
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45 .org 0
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46 #ifndef CONFIG_TARGET_COMPAL
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47 /* sane targets with Calypso boot ROM enabled by the PCB wiring */
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48 /* provide the necessary magic words for the boot ROM */
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49 .word 0
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50 .word _Firmware_boot_entry
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51 #elif defined(CONFIG_TARGET_C139) || defined(CONFIG_TARGET_C11X)
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52 /*
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53 * On this target we'll put a patched version of Compal's boot code in
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54 * flash sector 0 (the brickable one); the main fw images will then be
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55 * flashed starting at 0x10000, which is where our modified boot code
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56 * expects them to be. The interface between our hacked boot code and
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57 * the main fw has been made to mimic TI's TCS211 reference fw.
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58 */
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59 #include "vectors.S"
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60 .org 0x58 /* entry point at 0x10058 */
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61 b _Firmware_boot_entry
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62 #elif defined(CONFIG_TARGET_C155)
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63 /*
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64 * On this target the hand-off point between the bootloader and the main
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65 * fw image coincides with a flash erase block boundary, thus we can reuse
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66 * the original bootloader without having to reflash the brickable sector
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67 * at all. The following bits will appear at 0x20000.
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68 */
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69 .asciz "FreeCalypso firmware for C155/156 target"
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70 .org 0xE0
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71 /* C155/156 bootloader jumps here */
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72 b _Firmware_boot_entry
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73 #include "vectors.S"
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74 #else
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75 #error "Unsupported flash boot configuration"
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76 #endif
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77 #endif
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78
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79 /* definitions from TI's int.s */
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80
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81 #define IRQ_STACK_SIZE 128
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82 #define FIQ_STACK_SIZE 512
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83 #define SYSTEM_SIZE 1024
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84 #define TIMER_SIZE 1024
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85 #define TIMER_PRIORITY 2
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86
90
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87 @ TI's literal pool before the entry point
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88
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89 addrCS0: .word 0xfffffb00 @ CS0 address space
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90
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91 EX_MPU_CONF_REG: .word 0xFFFEF006 @ Extended MPU configuration register address
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92 EX_FLASH_VALUE: .short 0x0008 @ set bit to enable A22
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93
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94 .balign 4
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95
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96 CNTL_ARM_CLK_REG: .word 0xFFFFFD00 @ CNTL_ARM_CLK register address
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97 DPLL_CNTRL_REG: .word 0xFFFF9800 @ DPLL control register address
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98 EXTRA_CONTROL_REG: .word 0xFFFFFB10 @ Extra Control register CONF address
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99 MPU_CTL_REG: .word 0xFFFFFF08 @ MPU_CTL register address
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100
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101 CNTL_ARM_CLK_RST: .short 0x1081 @ Initialization of CNTL_ARM_CLK register
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102 @ Use DPLL, Divide by 1
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103 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state
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104 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module
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105 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module
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106 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled
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107
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108 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
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109 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
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110 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
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111 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable
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112 CS4_MEM_REG: .short 0xe85 @ default reset value
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113 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable
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114 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
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115 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation
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116
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117 .balign 4
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118
89
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119 .globl _Firmware_boot_entry
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 _Firmware_boot_entry:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 @ TI's code from int.s follows
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 @ Configure DPLL register with reset value
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 ldr r1,DPLL_CNTRL_REG @ Load address of DPLL register in R1
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 ldrh r2,DPLL_CONTROL_RST @ Load DPLL reset value in R2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 strh r2,[r1] @ Store DPLL reset value in DPLL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 @ Wait that DPLL goes in BYPASS mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 Wait_DPLL_Bypass:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 ldr r2,[r1] @ Load DPLL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 and r2,r2,#1 @ Perform a mask on bit 0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 cmp r2,#1 @ Compare DPLL lock bit
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 beq Wait_DPLL_Bypass @ Wait Bypass mode (i.e. bit[0]='0')
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 @ Configure CNTL_ARM_CLK register with reset value: DPLL is used to
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 @ generate ARM clock with division factor of 1.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 ldr r1,CNTL_ARM_CLK_REG @ Load address of CNTL_ARM_CLK register in R1
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 ldrh r2,CNTL_ARM_CLK_RST @ Load CNTL_ARM_CLK reset value in R2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 strh r2,[r1] @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 @ Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 ldr r1,EXTRA_CONTROL_REG @ Load address of Extra Control register CONF
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 ldrh r2,ENABLE_DU_MASK @ Load mask to write in Extra Control register CONF
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 ldrh r0,[r1] @ Load Extra Control register CONF in r0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 and r0,r0,r2 @ Enable DU module
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 strh r0,[r1] @ Store configuration in Extra Control register CONF
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 @ Disable all MPU protections
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 ldr r1,MPU_CTL_REG @ Load address of MPU_CTL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 ldrh r2,MPU_CTL_RST @ Load reset value of MPU_CTL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 strh r2,[r1] @ Store reset value of MPU_CTL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 @ MEMIF timing setup
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 ldr r1,addrCS0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 ldrh r2,CS0_MEM_REG @ ROM initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 strh r2,[r1] @ CS0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 ldrh r2,CS1_MEM_REG @ RAM Initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 strh r2,[r1,#2] @ CS1
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 ldrh r2,CS2_MEM_REG @ RAM Initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 strh r2,[r1,#4] @ CS2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 ldrh r2,CS3_MEM_REG @ Parallel I/O on B-Sample
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 strh r2,[r1,#6] @ CS3 (unused on EVA4?)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 ldrh r2,CS4_MEM_REG @ Latch on B-Sample
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 strh r2,[r1,#0xa] @ CS4 (unused on EVA4)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 ldrh r2,CS6_MEM_REG @ Internal SRAM initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 strh r2,[r1,#0xc] @ CS6 Internal RAM
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 ldrh r2,CS7_MEM_REG @ Internal SRAM initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 strh r2,[r1,#0x8] @ CS7 Internal Boot ROM
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 ldrh r2,CTL_MEM_REG @ API-RHEA configuration
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 strh r2,[r1,#0xe]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 @ enable ADD22
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 ldr r1,EX_MPU_CONF_REG
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 ldrh r2,[r1]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 ldr r0,EX_FLASH_VALUE
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 orr r0, r0, r2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 strh r0,[r1]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 /* Ensure that the processor is in supervisor mode. */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 ORR a1,a1,#LOCKOUT @ Ensure IRQ and FIQ interrupts are
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 @ locked out
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 MSR CPSR,a1 @ Setup the new CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 /*
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 * FreeCalypso Selenite: if this is a flash build,
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 * copy IRAM code and .data from flash to RAM.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 #ifdef FLASH
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 /* copy iram.text to where it's supposed to be */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 ldr r8, =__iramtext_flash_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 ldr r9, =__iramtext_ram_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 ldr r10, =__iramtext_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 1: ldmia r8!, {r0-r7}
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 stmia r9!, {r0-r7}
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 subs r10, r10, #0x20
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 bhi 1b
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 /* likewise copy .data from flash to XRAM */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 ldr r8, =__initdata_flash_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 ldr r9, =__initdata_ram_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 ldr r10, =__initdata_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 1: ldmia r8!, {r0-r7}
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 stmia r9!, {r0-r7}
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 subs r10, r10, #0x20
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 bhi 1b
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 #endif
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 /* Both flash and XRAM builds: zero .bss */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 ldr r0, =__intbss_start
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 ldr r1, =__intbss_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 bl bzero
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 ldr r0, =__extbss_start
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 ldr r1, =__extbss_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 bl bzero
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 @ TI's int.s code continues
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 @ Initialize the system stack pointers. This is done after the BSS is
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 @ cleared because the TCD_System_Stack pointer is a BSS variable! It is
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 @ assumed that the .cmd file is written to direct where these stacks should
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 @ be allocated and to align them on double word boundaries.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 LDR a1,StackSegment @ Pickup the begining address from .cmd file
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 @ (is aligned on 8 byte boundary)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 MOV a2,#SYSTEM_SIZE @ Pickup system stack size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 SUB a2,a2,#4 @ Subtract one word for first addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 ADD a3,a1,a2 @ Build start of system stack area
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 MOV v7,a1 @ Setup initial stack limit
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 LDR a4,System_Limit @ Pickup system stack limit address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 STR v7,[a4, #0] @ Save stack limit
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 MOV sp,a3 @ Setup initial stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 LDR a4,System_Stack @ Pickup system stack address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 STR sp,[a4, #0] @ Save stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 MOV a2,#IRQ_STACK_SIZE @ Pickup IRQ stack size in bytes
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 ADD a3,a3,a2 @ Allocate IRQ stack area
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 ORR a1,a1,#IRQ_MODE @ Set the IRQ mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 MSR CPSR,a1 @ Move to IRQ mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 MOV sp,a3 @ Setup IRQ stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 MOV a2,#FIQ_STACK_SIZE @ Pickup FIQ stack size in bytes
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 ADD a3,a3,a2 @ Allocate FIQ stack area
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 ORR a1,a1,#FIQ_MODE @ Set the FIQ mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 MSR CPSR,a1 @ Move to the FIQ mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 MOV sp,a3 @ Setup FIQ stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 ORR a1,a1,#ABORT_MODE @ Set the Abort mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 MSR CPSR,a1 @ Move to the Abort mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 LDR sp,Exception_Stack @ Setup Abort stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 ORR a1,a1,#UNDEF_MODE @ Set the Undefined mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 MSR CPSR,a1 @ Move to the Undefined mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 LDR sp,Exception_Stack @ Setup Undefined stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 @ (should never be used)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 @ go to Supervisor Mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 BIC a1,a1,#MODE_MASK @ Clear mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 MSR CPSR,a1 @ All interrupt stacks are setup,
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 @ return to supervisor mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 @ /* Define the global data structures that need to be initialized by this
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 @ routine. These structures are used to define the system timer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 @ management HISR. */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 @ TMD_HISR_Stack_Ptr = (VOID *) a3;
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 @ TMD_HISR_Stack_Size = TIMER_SIZE;
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 @ TMD_HISR_Priority = TIMER_PRIORITY;
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 @ TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 @ area. The Timer HISR (called "SYSTEM H") and its related stack will be created
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303 @ in TMI_Initialize(). The current stack pointer will be set at the bottom (the
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 @ lowest address) of the expected area.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 LDR a4,HISR_Stack_Ptr @ Pickup variable's address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 ADD a3,a3,#4 @ Increment to next available word
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 STR a3,[a4, #0] @ Setup timer HISR stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 MOV a2,#TIMER_SIZE @ Pickup the timer HISR stack size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 BIC a2,a2,#3 @ Insure word alignment
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 ADD a3,a3,a2 @ Allocate the timer HISR stack
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 @ from available memory
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 LDR a4,HISR_Stack_Size @ Pickup variable's address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 STR a2,[a4, #0] @ Setup timer HISR stack size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 MOV a2,#TIMER_PRIORITY @ Pickup timer HISR priority (0-2)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 LDR a4,HISR_Priority @ Pickup variable's address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 STR a2,[a4, #0] @ Setup timer HISR priority
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 /* TI's original code called f_load_int_mem() at this point */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 /* let's do our internal ROM enable step here */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 ldr r1, EXTRA_CONTROL_REG
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 ldrh r0, [r1, #0]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 bic r0, #0x0300
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 orr r0, #0x0100
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 strh r0, [r1, #0]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 @ We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 @ checking the status of the stacks later.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 @ inputs:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 @ a3 still has the bottom of all four stacks and is aligned.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 @ algorithm:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 @ We start from the top of all four stacks (*System_Limit), which is
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 @ necessarily aligned. We store 0xFEFEFEFE until we have filled the
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 @ bottom of the fourth stack
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 @ outputs:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 @ memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 @ a3 still has the bottom of all four stacks
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 LDR a2,System_Limit @ pickup system stack limit address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 LDR a1,[a2] @ a1 = StackSegment
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 LDR a4,=0xFEFEFEFE
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 fill_stack:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 STR a4,[a1],#4 @ store a word and increment by four
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 CMP a1,a3 @ is this the last address?
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 BLT fill_stack @ if not, loop back
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 @ /* Call INC_Initialize with a pointer to the first available memory
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 @ address after the compiler's global data. This memory may be used
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 @ by the application. */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 @ INC_Initialize(first_available_memory);
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 MOV a1,a3 @ Pass the first available memory
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 B INC_Initialize @ to high-level initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357
90
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
358 @ literal pool from int.s (after the code)
89
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 StackSegment:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 .word _Stack_segment_start
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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363 System_Limit:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
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364 .word TCT_System_Limit
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Mychaela Falconia <falcon@freecalypso.org>
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365
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366 System_Stack:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
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367 .word TCD_System_Stack
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Mychaela Falconia <falcon@freecalypso.org>
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368
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
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369 HISR_Stack_Ptr:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
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370 .word TMD_HISR_Stack_Ptr
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Mychaela Falconia <falcon@freecalypso.org>
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371
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Mychaela Falconia <falcon@freecalypso.org>
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372 HISR_Stack_Size:
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Mychaela Falconia <falcon@freecalypso.org>
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373 .word TMD_HISR_Stack_Size
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Mychaela Falconia <falcon@freecalypso.org>
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374
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
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375 HISR_Priority:
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Mychaela Falconia <falcon@freecalypso.org>
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376 .word TMD_HISR_Priority
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Mychaela Falconia <falcon@freecalypso.org>
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377
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
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378 Exception_Stack:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
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379 .word _Except_Stack_SP