FreeCalypso > hg > fc-selenite

comparison src/cs/system/main/gcc/bootentry.S @ 90:2de9e5f46550

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
.../main/gcc/bootentry.S: the literal pool needs to be arranged the way TI had it
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 20 Jul 2018 23:39:27 +0000
parents b398f288d20a
children 2c82c413775f
comparison
equal deleted inserted replaced
89:b398f288d20a 90:2de9e5f46550
55 * flashed starting at 0x10000, which is where our modified boot code 55 * flashed starting at 0x10000, which is where our modified boot code
56 * expects them to be. The interface between our hacked boot code and 56 * expects them to be. The interface between our hacked boot code and
57 * the main fw has been made to mimic TI's TCS211 reference fw. 57 * the main fw has been made to mimic TI's TCS211 reference fw.
58 */ 58 */
59 #include "vectors.S" 59 #include "vectors.S"
60 .org 0x58 /* put _Firmware_boot_entry at 0x10058 */ 60 .org 0x58 /* entry point at 0x10058 */
61 b _Firmware_boot_entry
61 #elif defined(CONFIG_TARGET_C155) 62 #elif defined(CONFIG_TARGET_C155)
62 /* 63 /*
63 * On this target the hand-off point between the bootloader and the main 64 * On this target the hand-off point between the bootloader and the main
64 * fw image coincides with a flash erase block boundary, thus we can reuse 65 * fw image coincides with a flash erase block boundary, thus we can reuse
65 * the original bootloader without having to reflash the brickable sector 66 * the original bootloader without having to reflash the brickable sector
80 #define IRQ_STACK_SIZE 128 81 #define IRQ_STACK_SIZE 128
81 #define FIQ_STACK_SIZE 512 82 #define FIQ_STACK_SIZE 512
82 #define SYSTEM_SIZE 1024 83 #define SYSTEM_SIZE 1024
83 #define TIMER_SIZE 1024 84 #define TIMER_SIZE 1024
84 #define TIMER_PRIORITY 2 85 #define TIMER_PRIORITY 2
86
87 @ TI's literal pool before the entry point
88
89 addrCS0: .word 0xfffffb00 @ CS0 address space
90
91 EX_MPU_CONF_REG: .word 0xFFFEF006 @ Extended MPU configuration register address
92 EX_FLASH_VALUE: .short 0x0008 @ set bit to enable A22
93
94 .balign 4
95
96 CNTL_ARM_CLK_REG: .word 0xFFFFFD00 @ CNTL_ARM_CLK register address
97 DPLL_CNTRL_REG: .word 0xFFFF9800 @ DPLL control register address
98 EXTRA_CONTROL_REG: .word 0xFFFFFB10 @ Extra Control register CONF address
99 MPU_CTL_REG: .word 0xFFFFFF08 @ MPU_CTL register address
100
101 CNTL_ARM_CLK_RST: .short 0x1081 @ Initialization of CNTL_ARM_CLK register
102 @ Use DPLL, Divide by 1
103 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state
104 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module
105 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module
106 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled
107
108 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
109 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
110 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
111 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable
112 CS4_MEM_REG: .short 0xe85 @ default reset value
113 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable
114 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
115 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation
116
117 .balign 4
85 118
86 .globl _Firmware_boot_entry 119 .globl _Firmware_boot_entry
87 _Firmware_boot_entry: 120 _Firmware_boot_entry:
88 @ TI's code from int.s follows 121 @ TI's code from int.s follows
89 122
320 @ INC_Initialize(first_available_memory); 353 @ INC_Initialize(first_available_memory);
321 @ 354 @
322 MOV a1,a3 @ Pass the first available memory 355 MOV a1,a3 @ Pass the first available memory
323 B INC_Initialize @ to high-level initialization 356 B INC_Initialize @ to high-level initialization
324 357
325 @ literal pool from int.s 358 @ literal pool from int.s (after the code)
326
327 addrCS0: .word 0xfffffb00 @ CS0 address space
328
329 EX_MPU_CONF_REG: .word 0xFFFEF006 @ Extended MPU configuration register address
330 EX_FLASH_VALUE: .short 0x0008 @ set bit to enable A22
331
332 CNTL_ARM_CLK_REG: .word 0xFFFFFD00 @ CNTL_ARM_CLK register address
333 DPLL_CNTRL_REG: .word 0xFFFF9800 @ DPLL control register address
334 EXTRA_CONTROL_REG: .word 0xFFFFFB10 @ Extra Control register CONF address
335 MPU_CTL_REG: .word 0xFFFFFF08 @ MPU_CTL register address
336
337 CNTL_ARM_CLK_RST: .short 0x1081 @ Initialization of CNTL_ARM_CLK register
338 @ Use DPLL, Divide by 1
339 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state
340 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module
341 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module
342 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled
343
344 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
345 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
346 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
347 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable
348 CS4_MEM_REG: .short 0xe85 @ default reset value
349 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable
350 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
351 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation
352 359
353 StackSegment: 360 StackSegment:
354 .word _Stack_segment_start 361 .word _Stack_segment_start
355 362
356 System_Limit: 363 System_Limit: