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annotate src/cs/system/template/gsm_ds_amd8_compact.template @ 179:2a9935250c95

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src/cs: sync with Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 04 Jan 2020 21:38:55 +0000
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179
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Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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2 * Integrated Protocol Stack Linker command file (all components)
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3 *
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4 * Target : ARM
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5 *
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6 * Copyright (c) Texas Instruments 2002, Condat 2002
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7 *
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8 */
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9
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10 -c /* Autoinitialize variables at runtime */
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11
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12 /*********************************/
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13 /* SPECIFY THE SYSTEM MEMORY MAP */
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14 /*********************************/
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15
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16 MEMORY
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17 {
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18 /* CS0: Flash 8 Mbytes ****************************************************/
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19 /* Interrupt Vectors Table */
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20 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
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21
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22 /* Boot Sector */
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23 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
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24
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25 /* Magic Word for Calypso Boot ROM */
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26 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
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27
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28 /* Program Memory */
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29 P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700
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30 P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004
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31 P_MEM3 (RXI) : org = 0x00004704 len = 0x00400000
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32
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33 /* FFS Area */
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34 FFS_MEM (RX) : org = 0x01800000 len = 0x00200000
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35 /**************************************************************************/
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36
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37 /* CS1: External SRAM 1 Mbytes ********************************************/
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38 /* Data Memory */
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39
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40 /*
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41 * FreeCalypso: we try to support several different Leonardo board
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42 * variants with different flash and XRAM sizes. In this template
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43 * we are going to define two XRAM regions of 1 MiB each.
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44 */
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45 D_MEM1 (RW) : org = 0x01000000 len = 0x00100000
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46 D_MEM2 (RW) : org = 0x01100000 len = 0x00100000
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47 /**************************************************************************/
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48
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49 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
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50 /* Code & Variables Memory */
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51 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
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52 /**************************************************************************/
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53 }
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54
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55 /***********************************************/
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56 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
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57 /***********************************************/
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58
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59 /*
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60 * Since the bootloader directly calls the INT_Initialize() routine located
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61 * in int.s, this int.s code must always be mapped at the same address
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62 * (usually in the second flash sector). Its length is about 0x500 bytes.
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63 * Then comes the code that need to be loaded into the internal RAM.
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64 */
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65
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66 SECTIONS
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67 {
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68 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
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69 .monitor : > B_MEM /* Monitor Constants & Code */
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70 {
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71 $(CONST_BOOT_LIB)
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72 }
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73
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74 .inttext : {} > P_MEM1 /* int.s Code */
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75
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76 .bss_dar : > D_MEM1 /* DAR SWE Variables */
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77 {
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78 $(BSS_DAR_LIB)
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79 }
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80
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81 /*
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82 * The .bss section should not be split to ensure it is initialized to 0
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83 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
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84 * or in D_MEM2.
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85 */
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86
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87 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
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88 {
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89 $(BSS_BOOT_LIB)
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90 }
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91
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92 /*
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93 * All .bss sections, which must be mapped in internal RAM must be
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94 * grouped in order to initialized the corresponding memory to 0.
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95 * This initialization is done in int.s file before calling the Nucleus
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96 * routine.
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97 */
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98
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99 GROUP
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100 {
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101 S_D_Mem /* Label of start address of .bss section in Int. RAM */
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102 .DintMem
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103 {
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104
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105 /*
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106 * .bss sections of the application
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107 */
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108
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109 $(BSS_LIBS)
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110
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111 }
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112
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113 API_HISR_stack : {}
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114
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115 E_D_Mem /* Label of end address of .bss section in Int. RAM */
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116 } > S_MEM
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117
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118 /*
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119 * .text and .const sections which must be mapped in internal RAM.
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120 */
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121
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122 .ldfl : {} > P_MEM2 /* Used to know the start load address */
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123 GROUP load = P_MEM3, run = S_MEM
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124 {
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125 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
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126 .PIntMem
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127 {
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128 /*
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129 * .text and .const sections of the application.
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130 *
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131 * The .veneer sections correspond exactly to .text:v&n sections
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132 * implementing the veneer functions. The .text:v$n -> .veneer
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133 * translation is performed by PTOOL software when PTOOL_OPTIONS
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134 * environement variable is set to veneer_section.
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135 */
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136
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137 $(CONST_LIBS)
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138
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139 }
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140 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
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141 }
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142
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143 /*
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144 * The rest of the code is mapped in flash, however the trampolines
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145 * load address should be consistent with .text.
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146 */
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147 COMMENT2START
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148 `trampolines load = P_MEM3, run = S_MEM
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149 COMMENT2END
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150
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151 .text : {} > P_MEM3 /* Code */
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152
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153 /*
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154 * The rest of the constants is mapped in flash.
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155 * The .cinit section should not be split.
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156 */
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157
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158 .cinit : {} > P_MEM3 /* Initialization Tables */
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159 .const : {} > P_MEM3 /* Constant Data */
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160 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
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161
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162 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
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163
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164 .stackandheap : > D_MEM1 /* System Stacks, etc... */
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165 {
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166 /* Leave 20 32bit words for register pushes. */
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167 . = align(8);
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168 . += 20 * 4;
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169
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170 /* Stack for abort and/or undefined modes. */
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171 exception_stack = .;
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172
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173 /* Leave 38 32bit words for state saving on exceptions. */
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174 _xdump_buffer = .;
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175 . += 38 * 4;
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176 . = align(8);
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177
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178 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
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179 stack_segment = .;
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180 . += 0xB00;
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181 }
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182
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183 .data : {} > D_MEM1 /* Initialized Data */
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184 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
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185
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186 }