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comparison src/cs/system/template/gsm_ds_amd8_compact.template @ 179:2a9935250c95

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src/cs: sync with Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 04 Jan 2020 21:38:55 +0000
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178:42edfb87ae0f 179:2a9935250c95
1 /*
2 * Integrated Protocol Stack Linker command file (all components)
3 *
4 * Target : ARM
5 *
6 * Copyright (c) Texas Instruments 2002, Condat 2002
7 *
8 */
9
10 -c /* Autoinitialize variables at runtime */
11
12 /*********************************/
13 /* SPECIFY THE SYSTEM MEMORY MAP */
14 /*********************************/
15
16 MEMORY
17 {
18 /* CS0: Flash 8 Mbytes ****************************************************/
19 /* Interrupt Vectors Table */
20 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
21
22 /* Boot Sector */
23 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
24
25 /* Magic Word for Calypso Boot ROM */
26 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
27
28 /* Program Memory */
29 P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700
30 P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004
31 P_MEM3 (RXI) : org = 0x00004704 len = 0x00400000
32
33 /* FFS Area */
34 FFS_MEM (RX) : org = 0x01800000 len = 0x00200000
35 /**************************************************************************/
36
37 /* CS1: External SRAM 1 Mbytes ********************************************/
38 /* Data Memory */
39
40 /*
41 * FreeCalypso: we try to support several different Leonardo board
42 * variants with different flash and XRAM sizes. In this template
43 * we are going to define two XRAM regions of 1 MiB each.
44 */
45 D_MEM1 (RW) : org = 0x01000000 len = 0x00100000
46 D_MEM2 (RW) : org = 0x01100000 len = 0x00100000
47 /**************************************************************************/
48
49 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
50 /* Code & Variables Memory */
51 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
52 /**************************************************************************/
53 }
54
55 /***********************************************/
56 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
57 /***********************************************/
58
59 /*
60 * Since the bootloader directly calls the INT_Initialize() routine located
61 * in int.s, this int.s code must always be mapped at the same address
62 * (usually in the second flash sector). Its length is about 0x500 bytes.
63 * Then comes the code that need to be loaded into the internal RAM.
64 */
65
66 SECTIONS
67 {
68 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
69 .monitor : > B_MEM /* Monitor Constants & Code */
70 {
71 $(CONST_BOOT_LIB)
72 }
73
74 .inttext : {} > P_MEM1 /* int.s Code */
75
76 .bss_dar : > D_MEM1 /* DAR SWE Variables */
77 {
78 $(BSS_DAR_LIB)
79 }
80
81 /*
82 * The .bss section should not be split to ensure it is initialized to 0
83 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
84 * or in D_MEM2.
85 */
86
87 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
88 {
89 $(BSS_BOOT_LIB)
90 }
91
92 /*
93 * All .bss sections, which must be mapped in internal RAM must be
94 * grouped in order to initialized the corresponding memory to 0.
95 * This initialization is done in int.s file before calling the Nucleus
96 * routine.
97 */
98
99 GROUP
100 {
101 S_D_Mem /* Label of start address of .bss section in Int. RAM */
102 .DintMem
103 {
104
105 /*
106 * .bss sections of the application
107 */
108
109 $(BSS_LIBS)
110
111 }
112
113 API_HISR_stack : {}
114
115 E_D_Mem /* Label of end address of .bss section in Int. RAM */
116 } > S_MEM
117
118 /*
119 * .text and .const sections which must be mapped in internal RAM.
120 */
121
122 .ldfl : {} > P_MEM2 /* Used to know the start load address */
123 GROUP load = P_MEM3, run = S_MEM
124 {
125 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
126 .PIntMem
127 {
128 /*
129 * .text and .const sections of the application.
130 *
131 * The .veneer sections correspond exactly to .text:v&n sections
132 * implementing the veneer functions. The .text:v$n -> .veneer
133 * translation is performed by PTOOL software when PTOOL_OPTIONS
134 * environement variable is set to veneer_section.
135 */
136
137 $(CONST_LIBS)
138
139 }
140 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
141 }
142
143 /*
144 * The rest of the code is mapped in flash, however the trampolines
145 * load address should be consistent with .text.
146 */
147 COMMENT2START
148 `trampolines load = P_MEM3, run = S_MEM
149 COMMENT2END
150
151 .text : {} > P_MEM3 /* Code */
152
153 /*
154 * The rest of the constants is mapped in flash.
155 * The .cinit section should not be split.
156 */
157
158 .cinit : {} > P_MEM3 /* Initialization Tables */
159 .const : {} > P_MEM3 /* Constant Data */
160 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
161
162 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
163
164 .stackandheap : > D_MEM1 /* System Stacks, etc... */
165 {
166 /* Leave 20 32bit words for register pushes. */
167 . = align(8);
168 . += 20 * 4;
169
170 /* Stack for abort and/or undefined modes. */
171 exception_stack = .;
172
173 /* Leave 38 32bit words for state saving on exceptions. */
174 _xdump_buffer = .;
175 . += 38 * 4;
176 . = align(8);
177
178 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
179 stack_segment = .;
180 . += 0xB00;
181 }
182
183 .data : {} > D_MEM1 /* Initialized Data */
184 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
185
186 }