changeset 604:a7ed7d4483b0

main assembly boot path code: MEMIF change for 26 MHz targets as explained in the MEMIF-wait-states document
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 02:11:17 +0000
parents b13731665274
children 07d0dc4431f4
files components/main components/main-init src/cs/system/main/init.asm
diffstat 3 files changed, 24 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/components/main	Mon Jun 17 01:36:38 2019 +0000
+++ b/components/main	Mon Jun 17 02:11:17 2019 +0000
@@ -77,4 +77,11 @@
 	ASMFLAGS="$ASMFLAGS -dC155_TARGET=0"
 fi
 
+if [ "$RF" = 12 ]
+then
+	ASMFLAGS="$ASMFLAGS -dVCXO_26MHZ=1"
+else
+	ASMFLAGS="$ASMFLAGS -dVCXO_26MHZ=0"
+fi
+
 asm_file $SRCDIR/int.s
--- a/components/main-init	Mon Jun 17 01:36:38 2019 +0000
+++ b/components/main-init	Mon Jun 17 02:11:17 2019 +0000
@@ -85,4 +85,11 @@
 	ASMFLAGS="$ASMFLAGS -dC155_TARGET=0"
 fi
 
+if [ "$RF" = 12 ]
+then
+	ASMFLAGS="$ASMFLAGS -dVCXO_26MHZ=1"
+else
+	ASMFLAGS="$ASMFLAGS -dVCXO_26MHZ=0"
+fi
+
 asm_file $SRCDIR/int.s
--- a/src/cs/system/main/init.asm	Mon Jun 17 01:36:38 2019 +0000
+++ b/src/cs/system/main/init.asm	Mon Jun 17 02:11:17 2019 +0000
@@ -170,9 +170,19 @@
 
   .elseif BOARD = 41
 
+; FreeCalypso change, please see MEMIF-wait-states document
+; in the freecalypso-docs repository for the explanation.
+
+    .if VCXO_26MHZ = 1
+CS0_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+CS1_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+CS2_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+    .else
 CS0_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
 CS1_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
 CS2_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
+    .endif
+
 CS3_MEM_REG   .short  0x283  ; 1 Dummy Cycle  8 bit 3 WS SW BP enable
 CS4_MEM_REG   .short  0xe85  ; default reset value