FCDEV3B status update

[Mychaela Falconia]

Hello everyone,

Another set of updates on the quest to turn our FCDEV3B hardware
design into reality:

* Unfortunately my anonymous off-list contacts have gone silent once
  again.  The last email I got from them was on May 3, and the only
  thing my contact wanted to talk about was their GTA02 issues - they
  have managed to acquire some Openmoko-made GTA02 units somehow,
  despite them being completely unavailable to everyone else, they
  seem to have adopted the GTA02 as their sole platform of interest,
  and they were seeking extensive hand-holding from me with their
  issues with GTA02 AP software, while telling me as little as possible
  as to what they were actually trying to accomplish.  Meanwhile they
  kept evading any discussion of FCDEV3B: the last email I got from
  them regarding FCDEV3B was on Apr 29, and all emails in the Apr 30 -
  May 3 window were only about their GTA02 issues, with my FCDEV3B
  concerns completely ignored.

  So I feel that it is time to conclude that the anonymous off-list
  folks have decided to abandon our community to focus solely on their
  own self-interest instead, and we are entirely on our own from here
  onward.

* The state of the FCDEV3B PCB design: I *thought* that the design was
  good and ready to go out to fab, but it turned out otherwise.  One
  of the several PCB fabs from which I sought fabrication price quotes
  came back to me with a report highlighting a serious problem in the
  design that absolutely must be fixed before fabrication.

All PCBs have what are called design rules, and two very critical
rules (which are often stated as one) are called minimum trace and
minimum space.  The minimum trace rule gives the minimum width which
any trace or other copper feature on the board is allowed to have, and
the minimum space rule gives the minimum required space between any
two different copper features.  Both are typically measured in mils or
decimal fractions of a millimetre, depending on which units-of-
measurement culture you are in.

Openmoko's GTA02 PCB was designed in mils and has 4 mil trace/space
rules, which is equivalent to 0.10 mm rules for metric-based PCB fabs.
Being a direct derivative of the GTA02, FCDEV3B has to have the same
rules.  As far as the new layout and routing goes (that which was done
specifically for FCDEV3B), I have not seen any violations of these
rules, i.e., I don't see any spots where they tried to make a trace
narrower than 4 mils or squeeze traces or other features together with
less than 4 mils of separation.  However, what the PCB fab highlighted
for me were numerous spots where the minimum space rule is inadvertently
violated because of lack of attention to GND pour clearance settings.

Like all existing Calypso-era cellular boards I have seen, including
the GTA02, our FCDEV3B has copper pours, i.e., all unused space on all
layers is flooded with GND copper instead of being left free.  As
non-GND component pads and interconnecting traces are placed on each
layer, they create auto-generated clearances around themselves in the
GND copper pour, and eventually the originally-solid pour ends up
being broken into isolated islands, which have to be electrically
connected by way of vias to other layers in order to form a single
continuous ground.  The shape of these individual GND pour islands is
odd and irregular, determined by the placement of non-GND copper
objects around them and the auto-generated clearances.

But when the PCB design tool auto-generates these odd shapes for GND
pour islands, how does it know exactly how far away it needs to stay
from the surrounding non-GND copper objects?  The answer is that there
must be a setting in the tool somewhere that tells it how large this
clearance needs to be.  It could be implemented as a global setting,
as a property of the GND pour or as properties of the non-GND copper
objects it needs to stay away from, but however it is implemented in
any given PCB design tool, the configurable setting must exist in some
form.

The problem with our current FCDEV3B gerber files (the ones dated
20160423) is that the auto-generated clearances between GND copper
pours and non-GND copper objects are too small: they seem to be
somewhere around 1 or 2 mils, whereas they need to be 4 mils by the
minimum space rule.  So it looks like whatever setting in Altium
controls these auto-generated clearances must have got set wrong
somehow.

Thus we are back to needing someone who works with Altium PCB design
software to fix this defect for us.  Right now I am trying to get help
from www.911eda.com - they are a PCB design consulting company in my
local area.  I first emailed them on Friday, then on Monday after
hearing nothing I called them on the phone and was told to resend my
email to a specific person there.  This morning (Wednesday) I called
them again and got that same person on the phone, he told me that he
got my email, but they have been busy; he told me that he may be able
to find some time to look at it today.  What I need to get from them
is a price quote for their labor to fix the critical defect in our
design; once I have this price quote, I will need to add it to the
other costs of physically producing the first batch of boards (I
detailed them in my previous post in this thread last week) and use
the revised total cost to plan the crowdfunding campaign accordingly.

I am now waiting for that price quote from 911EDA - please stay tuned
for further updates.

M~