FreeCalypso > hg > freecalypso-tools

annotate target-utils/libbase/spidrv.c @ 496:3d73d4d3527f

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target-utils: removed osmo_delay_ms() from ABB access code
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 25 May 2019 20:17:27 +0000
parents e7502631a0f9
children
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Mychaela Falconia <falcon@freecalypso.org>
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1 /* Driver for SPI Master Controller inside TI Calypso */
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2 /* lifted from OsmocomBB and ported to FreeCalypso target-utils environment */
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3
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4 /* (C) 2010 by Harald Welte <laforge@gnumonks.org>
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5 *
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6 * All Rights Reserved
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7 *
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8 * This program is free software; you can redistribute it and/or modify
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9 * it under the terms of the GNU General Public License as published by
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10 * the Free Software Foundation; either version 2 of the License, or
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Mychaela Falconia <falcon@freecalypso.org>
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11 * (at your option) any later version.
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12 *
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Mychaela Falconia <falcon@freecalypso.org>
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13 * This program is distributed in the hope that it will be useful,
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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Mychaela Falconia <falcon@freecalypso.org>
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16 * GNU General Public License for more details.
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17 *
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18 * You should have received a copy of the GNU General Public License along
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Mychaela Falconia <falcon@freecalypso.org>
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19 * with this program; if not, write to the Free Software Foundation, Inc.,
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20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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21 *
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22 */
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23
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24 #include "types.h"
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25
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26 #define ASIC_CONF_REG (*(volatile u16 *) 0xFFFEF008)
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27
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28 struct spi_regs {
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29 u16 reg_set1;
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30 u16 reg_set2;
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31 u16 reg_ctrl;
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32 u16 reg_status;
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33 u16 reg_tx_lsb;
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34 u16 reg_tx_msb;
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35 u16 reg_rx_lsb;
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36 u16 reg_rx_msb;
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37 };
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38
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39 #define SPI_REGS (*(volatile struct spi_regs *) 0xFFFE3000)
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40
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41 #define BASE_ADDR_SPI 0xfffe3000
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42 #define SPI_REG(n) (BASE_ADDR_SPI+(n))
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43
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44 #define SPI_SET1_EN_CLK (1 << 0)
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45 #define SPI_SET1_WR_IRQ_DIS (1 << 4)
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46 #define SPI_SET1_RDWR_IRQ_DIS (1 << 5)
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47
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48 #define SPI_CTRL_RDWR (1 << 0)
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49 #define SPI_CTRL_WR (1 << 1)
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50 #define SPI_CTRL_NB_SHIFT 2
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51 #define SPI_CTRL_AD_SHIFT 7
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52
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53 #define SPI_STATUS_RE (1 << 0) /* Read End */
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54 #define SPI_STATUS_WE (1 << 1) /* Write End */
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55
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56 spi_init()
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57 {
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58 static int initdone;
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59
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60 if (initdone)
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61 return(0);
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62 ASIC_CONF_REG |= 0x6000;
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63 SPI_REGS.reg_set1 = SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS |
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64 SPI_SET1_RDWR_IRQ_DIS;
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65 SPI_REGS.reg_set2 = 0x0001;
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66 initdone = 1;
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67 return(1);
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68 }
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69
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70 spi_xfer(dev_idx, bitlen, dout, din)
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71 void *dout, *din;
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72 {
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73 int bytes_per_xfer;
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74 u16 reg_status, reg_ctrl = 0;
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75 u32 tmp;
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76
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77 if (bitlen <= 0)
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78 return 0;
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79
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80 if (bitlen > 32)
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81 return -1;
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82
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83 if (dev_idx > 4)
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84 return -1;
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85
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86 bytes_per_xfer = bitlen / 8;
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87 if (bitlen % 8)
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88 bytes_per_xfer ++;
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89
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90 reg_ctrl |= (bitlen - 1) << SPI_CTRL_NB_SHIFT;
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91 reg_ctrl |= (dev_idx & 0x7) << SPI_CTRL_AD_SHIFT;
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92
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93 if (bitlen <= 8) {
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94 tmp = *(u8 *)dout;
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95 tmp <<= 24 + (8-bitlen); /* align to MSB */
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96 } else if (bitlen <= 16) {
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97 tmp = *(u16 *)dout;
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98 tmp <<= 16 + (16-bitlen); /* align to MSB */
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99 } else {
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100 tmp = *(u32 *)dout;
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101 tmp <<= (32-bitlen); /* align to MSB */
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102 }
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103
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104 /* fill transmit registers */
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105 SPI_REGS.reg_tx_msb = tmp >> 16;
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106 SPI_REGS.reg_tx_lsb = tmp;
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107
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108 /* initiate transfer */
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109 if (din)
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110 reg_ctrl |= SPI_CTRL_RDWR;
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111 else
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112 reg_ctrl |= SPI_CTRL_WR;
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113 SPI_REGS.reg_ctrl = reg_ctrl;
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114
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115 /* wait until the transfer is complete */
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diff changeset
116 while (1) {
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117 reg_status = SPI_REGS.reg_status;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118 if (din && (reg_status & SPI_STATUS_RE))
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 break;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 else if (reg_status & SPI_STATUS_WE)
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 break;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 }
496
3d73d4d3527f target-utils: removed osmo_delay_ms() from ABB access code
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
123 /* delay of seven 13MHz cycles */
3d73d4d3527f target-utils: removed osmo_delay_ms() from ABB access code
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
124 wait_ARM_cycles(7);
0
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 if (din) {
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 tmp = SPI_REGS.reg_rx_msb << 16;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 tmp |= SPI_REGS.reg_rx_lsb;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 if (bitlen <= 8)
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 *(u8 *)din = tmp & 0xff;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 else if (bitlen <= 16)
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 *(u16 *)din = tmp & 0xffff;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 else
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 *(u32 *)din = tmp;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 }
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 return 0;
e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 }