FreeCalypso > hg > freecalypso-sw
changeset 576:660e83f13cab
gsm-fw/L1/tpudrv: tpudrv.c and tpudrv61.[ch] imported from LoCosto source
| author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
|---|---|
| date | Mon, 11 Aug 2014 04:45:42 +0000 |
| parents | 1d7a12925b8e |
| children | d70ebaea3003 |
| files | gsm-fw/L1/tpudrv/tpudrv.c gsm-fw/L1/tpudrv/tpudrv61.c gsm-fw/L1/tpudrv/tpudrv61.h |
| diffstat | 3 files changed, 3200 insertions(+), 0 deletions(-) [+] |
line wrap: on
line diff
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/L1/tpudrv/tpudrv.c Mon Aug 11 04:45:42 2014 +0000 @@ -0,0 +1,578 @@ +/************* Revision Controle System Header ************* + * GSM Layer 1 software + * + * Filename tpudrv.c + * Copyright 2003 (C) Texas Instruments + * + ************* Revision Controle System Header *************/ +/* + * TPUDRV.C + * + * TPU driver for Pole Star + * + * + * Copyright (c) Texas Instruments 1996 + * + */ + +#include "l1_macro.h" +#include "iq.h" +#include "l1_confg.h" +#include "l1_const.h" +#include "l1_types.h" + +#if (AUDIO_TASK == 1) + #include "l1audio_const.h" + #include "l1audio_cust.h" + #include "l1audio_defty.h" +#endif + +#if (L1_GTT == 1) + #include "l1gtt_const.h" + #include "l1gtt_defty.h" +#endif + +#if (L1_MIDI == 1) + #include "l1midi_defty.h" +#endif + +#include "sys_types.h" + +#if TESTMODE + #include "l1tm_defty.h" +#endif + +#if (L1_MP3 == 1) + #include "l1mp3_defty.h" +#endif + +#if (L1_MIDI == 1) + #include "l1midi_defty.h" +#endif + +#if (L1_AAC == 1) + #include "l1aac_defty.h" +#endif +#include "l1_defty.h" +#include "tpudrv.h" +#include "sys_types.h" +#include "clkm.h" +#include "l1_time.h" +#include "l1_varex.h" +#include "l1_trace.h" + +#if (L1_MADC_ON == 1) +#if (RF_FAM == 61) +#include "drp_api.h" +#include "l1_rf61.h" +#include "drp_drive.h" +#include "tpudrv61.h" +extern T_DRP_REGS_STR *drp_regs; +#endif +#endif //L1_MADC_ON + +/* RFTime environment */ +#if defined (HOST_TEST) + #include "hostmacros.h" +#endif + + +/* + * VEGA and OMEGA receive windows - Defined in Customer-specific file + */ + +extern UWORD32 debug_tpu; + +#if ( OP_WCP == 1 ) && ( OP_L1_STANDALONE != 1 ) + // WCS Patch : ADC during RX or TX + extern inline void GC_SetAdcInfo(unsigned char bTxBasedAdc); +#endif + +/* + * Global Variables + */ +// GSM1.5 : TPU MEMORY is 16-bit instead of 32 in Gemini/Polxx +//------------------------------------------------------------ +SYS_UWORD16 *TP_Ptr = (SYS_UWORD16 *) TPU_RAM; + + +/*--------------------------------------------------------------*/ +/* TPU_Reset : Reset the TPU */ +/*--------------------------------------------------------------*/ +/* Parameters : on/off(1/0) */ +/* Return : none */ +/* Functionality : ) Reset the TPU */ +/*--------------------------------------------------------------*/ +void TPU_Reset(SYS_UWORD16 on) +{ + if (on) + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_RESET; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET)); + } + else + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_RESET; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET)); + } +} + +/*--------------------------------------------------------------*/ +/* TSP_Reset : Reset the TSP */ +/*--------------------------------------------------------------*/ +/* Parameters : on/off(1/0) */ +/* Return : none */ +/* Functionality : ) Reset the TSP */ +/*--------------------------------------------------------------*/ +void TSP_Reset(SYS_UWORD16 on) +{ + if (on) + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TSP_CTRL_RESET; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET)); + } + else + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TSP_CTRL_RESET; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET)); + } +} + +/*--------------------------------------------------------------*/ +/* TPU_SPIReset : Reset the SPI of the TPU */ +/*--------------------------------------------------------------*/ +/* Parameters : on/off(1/0) */ +/* Return : none */ +/* Functionality : ) the SPI of the TPU */ +/*--------------------------------------------------------------*/ + +void TPU_SPIReset(SYS_UWORD16 on) +{ + if (on) + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_SPI_RST; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST)); + } + else + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_SPI_RST; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST)); + } +} + +/*--------------------------------------------------------------*/ +/* TPU_ClkEnable : */ +/*--------------------------------------------------------------*/ +/* Parameters : on/off(1/0) */ +/* Return : none */ +/* Functionality : Enable the TPU clock */ +/*--------------------------------------------------------------*/ + +void TPU_ClkEnable(SYS_UWORD16 on) +{ + if (on) + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_CLK_EN; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN)); + } + else + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_CLK_EN; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN)); + } +} + +/*--------------------------------------------------------------*/ +/* TPU_Frame_ItOn : */ +/*--------------------------------------------------------------*/ +/* Parameters : bit of it to enable */ +/* Return : none */ +/* Functionality : Enable frame it */ +/*--------------------------------------------------------------*/ + +/*-----------------------------------------------------------*/ +/* Warning read modify write access to TPU_INT_CTRL register */ +/* may generate problems using Hyperion. */ +/*-----------------------------------------------------------*/ + +void TPU_FrameItOn(SYS_UWORD16 it) +{ + * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) &= ~it; +} + +void TPU_FrameItEnable(void) +{ + #if W_A_ITFORCE + (*(volatile SYS_UWORD16 *)TPU_INT_CTRL) |= TPU_INT_ITD_F; + #else + // enable IT_DSP generation on next frame + // reset by DSP when IT occurs + (*(volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_D_ENBL; + // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso + while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL)); + #endif +} + +/*--------------------------------------------------------------*/ +/* TPU_check_IT_DSP : */ +/*--------------------------------------------------------------*/ +/* Parameters : none */ +/* Return : none */ +/* Functionality : check if an IT DSP still pending */ +/*--------------------------------------------------------------*/ +BOOL TPU_check_IT_DSP(void) +{ // return TRUE if an IT DSP still pending. + return( (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL) == TPU_CTRL_D_ENBL)); +} + +/*--------------------------------------------------------------*/ +/* TPU_DisableAllIt : */ +/*--------------------------------------------------------------*/ +/* Parameters : none */ +/* Return : none */ +/* Functionality : Disabl all it */ +/*--------------------------------------------------------------*/ +void TPU_DisableAllIt() +{ + * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) |= TPU_INT_ITF_M | TPU_INT_ITP_M | TPU_INT_ITD_M; + +} + + + + + +/* + * TP_Program + * + * Write a null-terminated scenario into TPU memory at a given start address + * (Do not write terminating 0) + * + */ +void *TP_Program(const SYS_UWORD16 *src) +{ + /* Write TPU instructions until SLEEP */ + while (*src) + { + *TP_Ptr++ = *src++; + } + #if (TOOL_CHOICE == 3) // 2.54 Migration + return((void *)NULL); + #endif // TOOL_CHOICE == 3 + // return((void *)NULL);//ompas00090550 + +} + + + +void TP_Reset(SYS_UWORD16 on) +{ + if (on) { + * ((volatile SYS_UWORD16 *) TPU_CTRL) |= (TPU_CTRL_RESET | TSP_CTRL_RESET); + while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET))); + } + else { + * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~(TPU_CTRL_RESET | TSP_CTRL_RESET); + while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET))); + } +} + +void TP_Enable(SYS_UWORD16 on) +{ + if(on) + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_T_ENBL; + + // Some time shall be wait before leaving the function to ensure that bit has been taken + // in account by the TPU. A while loop such as in function TP_reset can't be used as the + // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781). + // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU. + // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin. + wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us + } + else + { + * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_T_ENBL; + // Some time shall be wait before leaving the function to ensure that bit has been taken + // in account by the TPU. A while loop such as in function TP_reset can't be used as the + // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781). + // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU. + // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin. + wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us + } +} + + +/*-----------------------------------------------------------------------*/ +/* Function name: TPU_wait_idle */ +/*-----------------------------------------------------------------------*/ +/* */ +/* Parameters: None */ +/* */ +/* Return: None */ +/* */ +/*-----------------------------------------------------------------------*/ +/* Description: Wait until TPU scenario execution is complete */ +/* */ +/*-----------------------------------------------------------------------*/ +void TPU_wait_idle(void) +{ + while( ((*(volatile SYS_UWORD16 *) (TPU_CTRL)) & TPU_CTRL_TPU_IDLE) == TPU_CTRL_TPU_IDLE) + { + wait_ARM_cycles(convert_nanosec_to_cycles(3000)); + } +} + + +/* + * l1dmacro_idle + * + * Write SLEEP instruction, start TPU and reset pointer + */ +void l1dmacro_idle (void) +{ + *TP_Ptr++ = TPU_SLEEP; + + /* start TPU */ + TP_Ptr = (SYS_UWORD16 *) TPU_RAM; + TP_Enable(1); +} + +/* + * l1dmacro_offset + * + * Set OFFSET register + * + */ +void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time) +{ + // WARNING: 'relative time' and 'offset_value' must always be comprised + // between 0 and TPU_CLOCK_RANGE !!! + + if (relative_time != IMM) // IMM indicates to set directly without AT + { + *TP_Ptr++ = TPU_FAT(relative_time); + } + *TP_Ptr++ = TPU_OFFSET(offset_value); +} + +/* + * l1dmacro_synchro + * + * Set synchro register + */ +void l1dmacro_synchro (UWORD32 when, UWORD32 value) +{ + // WARNING: 'when' must always be comprised between 0 and TPU_CLOCK_RANGE !!! + #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5) + trace_fct(CST_L1DMACRO_SYNCHRO, 1);//omaps00090550 + #endif + + if (value != IMM) // IMM indicates to set directly without AT + { + *TP_Ptr++ = TPU_FAT(when); + } + + *TP_Ptr++ = TPU_SYNC(value); + l1s.tpu_offset_hw = value; // memorize the offset set into the TPU. +} + + +/* + * l1dmacro_adc_read + * + */ +void l1dmacro_adc_read_rx(void) +{ + + #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) + // TSP needs to be configured in order to send serially to Omega + +// *TP_Ptr++ = TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE); // Clock configuration + *TP_Ptr++ = TPU_WAIT (5); + *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration + *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,STARTADC); // Load data to send + *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion + *TP_Ptr++ = TPU_WAIT (5); + *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,0x00); + *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse + + #if (TRACE_TYPE==1)||(TRACE_TYPE ==4) + #if (GSM_IDLE_RAM == 0) + l1_trace_ADC(0); + #else + l1_trace_ADC_intram(0); + #endif + #endif + #endif + +#if (L1_MADC_ON == 1) + #if (ANLG_FAM == 11) + + #if (TRACE_TYPE==1)||(TRACE_TYPE ==4) + #if (GSM_IDLE_RAM == 0) + l1_trace_ADC(0); + #else + l1_trace_ADC_intram(0); + #endif + #endif + #endif + + #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1) + // WCS patch: ADC during RX + GC_SetAdcInfo(0); + #endif +#endif +} + + +#if (CODE_VERSION != SIMULATION) +#if (L1_MADC_ON ==1) +/* + * l1dmacro_adc_read_rx_cs_mode0 + * + * Purpose: + * ====== + * MADC is not enabled during CS_MODE0 periodically. MADC is enabled in CS_MODE0 + * when Layer 1 receives MPHC_RXLEV_REQ from L23. However in CS_MODE0, MPHC_RXLEV_REQ + * is not received periodically. In case network is not found, the period between 2 MPHC_RXLEV_REQ + * increases and can be as high as 360 seconds (Maximum Value) + * This can result in battery related issues like phone powering off without MMI indication. + */ + + +void l1dmacro_adc_read_rx_cs_mode0(void) +{ + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC); + *TP_Ptr++ = TPU_WAIT (2); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,0); + +#if (L1_MADC_ON == 1) + #if (ANLG_FAM == 11) + + #if (TRACE_TYPE==1)||(TRACE_TYPE ==4) + #if (GSM_IDLE_RAM == 0) + l1_trace_ADC(0); + #else + l1_trace_ADC_intram(0); + #endif + #endif + #endif + + #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1) + // WCS patch: ADC during RX + GC_SetAdcInfo(0); + #endif +#endif +} + + +#endif //If MADC is enabled +#endif //If Not Simulation + +/* + * l1dmacro_adc_read_tx + * + */ + + +#if (ANLG_FAM != 11) +void l1dmacro_adc_read_tx(UWORD32 when) +#else +void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state) +#endif +{ + + #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) + + *TP_Ptr++ = TPU_FAT (when); + *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration + *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, STARTADC|BULON|BULENA); // Load data to send + *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion + *TP_Ptr++ = TPU_WAIT (5); + *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, BULON|BULENA); + *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse + + #if (TRACE_TYPE==1)||(TRACE_TYPE ==4) + l1_trace_ADC(1); + #endif + #endif + +#if (L1_MADC_ON == 1) + #if (ANLG_FAM == 11) + *TP_Ptr++ = TPU_FAT (when); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC); + *TP_Ptr++ = TPU_WAIT (2); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state); + +#if 1 // TEMP MEASUREMENT - uncomment and test after MADC +#if (RF_FAM == 61) + *TP_Ptr++ = TPU_MOVE(OCP_DATA_MSB, ((START_SCRIPT(DRP_TEMP_CONV))>>8) & 0xFF); \ + *TP_Ptr++ = TPU_MOVE(OCP_DATA_LSB, (START_SCRIPT(DRP_TEMP_CONV)) & 0xFF); \ + *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_MSB, (((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)>>8) & 0xFF)); \ + *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_LSB, ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)) & 0xFF); \ + *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_START, 0x01); \ + //TEMP_MEAS: Call TEMP Conv Script in DRP + //MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TEMP_CONV),(UWORD16)(&drp_regs->SCRIPT_STARTL)); +#endif + +#endif + + #if (TRACE_TYPE==1)||(TRACE_TYPE ==4) + l1_trace_ADC(1); + #endif + + #endif +#endif //L1_MADC_ON + + #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1) + // WCS patch: ADC during TX + GC_SetAdcInfo(1); + #endif + + +} + + +/* +#if (RF_FAM == 61) + +void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state) +{ + int i; + + *TP_Ptr++ = TPU_FAT (when); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC); + *TP_Ptr++ = TPU_WAIT (2); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state); + + #if (TRACE_TYPE==1)||(TRACE_TYPE ==4) + l1_trace_ADC(1); + #endif + + + #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1) + // WCS patch: ADC during TX + GC_SetAdcInfo(1); + #endif +} + +#endif +*/ + +/* + * l1dmacro_set_frame_it + * + */ +void l1dmacro_set_frame_it(void) +{ + TPU_FrameItEnable(); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/L1/tpudrv/tpudrv61.c Mon Aug 11 04:45:42 2014 +0000 @@ -0,0 +1,2163 @@ +/****************** Revision Controle System Header *********************** + * GSM Layer 1 software + * Copyright (c) Texas Instruments 1998 + * + * Filename tpudrv61.c + * Version 1.0 + * Date May 27th, 2005 + * + ****************** Revision Controle System Header ***********************/ + +#define TPUDRV61_C + +#include "rf.cfg" +#include "drp_api.h" + +#include "l1_macro.h" +#include "l1_confg.h" +#include "l1_const.h" +#include "l1_types.h" +#if TESTMODE + #include "l1tm_defty.h" +#endif +#if (AUDIO_TASK == 1) + #include "l1audio_const.h" + #include "l1audio_cust.h" + #include "l1audio_defty.h" +#endif +#if (L1_GTT == 1) + #include "l1gtt_const.h" + #include "l1gtt_defty.h" +#endif +#if (L1_MP3 == 1) + #include "l1mp3_defty.h" +#endif +#if (L1_MIDI == 1) + #include "l1midi_defty.h" +#endif + +#if (L1_AAC == 1) + #include "l1aac_defty.h" +#endif + +#include "l1_defty.h" +#include "l1_time.h" +#include "l1_ctl.h" +#include "tpudrv.h" +#include "tpudrv61.h" +#include "l1_rf61.h" + +#include "mem.h" + +#include "armio.h" +#include "clkm.h" + +#if (L1_RF_KBD_FIX == 1) +#include "l1_varex.h" +#endif + +extern const UWORD8 drp_ref_sw[] ; +extern T_DRP_REGS_STR *drp_regs; +extern T_DRP_SRM_API* drp_srm_api; + + +// Global variables +extern T_L1_CONFIG l1_config; +extern UWORD16 AGC_TABLE[]; +extern UWORD16 *TP_Ptr; +#if (L1_FF_MULTIBAND == 1) +extern const WORD8 rf_subband2band[RF_NB_SUBBANDS]; +#endif + +static WORD8 rf_index; // index into rf_path[] + +#if( L1_TPU_DEV == 1) +WORD16 rf_rx_tpu_timings[NB_TPU_TIMINGS] = +{ +// - RX up: +// The times below are offsets to when the 1st bit is at antenna +// Burst data comes here + (PROVISION_TIME - 203 - DLT_4B - rdt ), // TRF_R1 Set RX Synth channel + //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst + (PROVISION_TIME - 197 - DLT_4B - rdt ), // TRF_R2 Select the AGC & LNA gains + (PROVISION_TIME - 190 - DLT_4B - rdt ) , // TRF_R3 RX_ON + (PROVISION_TIME - 39 - DLT_1 - rdt ), // TRF_R4 Set RF switch for RX in selected band + (PROVISION_TIME - 19 - DLT_1), // TRF_R5 Enable RX_START + ( -20 - DLT_4B ), // TRF_R6 Disable RX Start and RF switch + // TRF_R6 not use, warning timing TRF_R6 > TRF_R7 + ( 2 - DLT_4B), // TRF_R7 Power down RF (idle script) + #if (L1_MADC_ON == 1) + (PROVISION_TIME - 170 - DLT_4B - rdt ), // for doing MADC + #else + 0, + #endif + 0, + 0, + 0, 0,0,0,0,0,0,0,0,0, + 0, 0,0,0,0,0,0,0,0,0, + 0,0 +}; + +WORD16 rf_tx_tpu_timings[NB_TPU_TIMINGS] = +{ +// - TX up: +// The times below are offsets to when TXSTART goes high +//burst data comes here + ( - 255 - DLT_4B - tdt ), // TRF_T1 Set TX synth + ( - 235 - DLT_4B - tdt ), // TRF_T2 Power ON TX + ( - 225 - DLT_1 ), // TRF_T3 + ( - 100 - DLT_1 ), // TRF_T4 + ( - 30 - DLT_1 ), // TRF_T5 + ( 0 - DLT_1 ), // TRF_T6 + ( 8 - DLT_1 ), // TRF_T7 + ( 16 - DLT_1 ), // TRF_T8 + // - TX timings --- +// - TX down: +// The times below are offsets to when TXSTART goes down + ( - 40 - DLT_1 ), // TRF_T9 ADC read + ( 0 - DLT_1 ), // TRF_T10 Disable APC + ( 16 - DLT_1 ) , // TRF_T11 Disable PA + ( 20 - DLT_1 ) , // TRF_T12 Disable TXSTART + ( 30 - DLT_4B ) , // TRF_T13 Power off Locosto + 0, + 0, + 0, + 0, + 0,0,0, + 0, 0,0,0,0,0,0,0,0,0, + 0,0 +}; + +//Flexi ABB DELAYS +WORD16 rf_flexi_abb_delays[NB_ABB_DELAYS] = { +//Note: 0th element is not mapped to anything should be always 0 +0, 20, (45L), 12, 0 , 0 , 0 , 12, 5, 6, +1L, (63L + 4L), (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY), 2L, 20L, 10L, 20, 6, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0 +}; + +#endif //TPU_DEVEL + +// Internal function prototypes +void l1dmacro_rx_down (WORD32 t); + +#if (L1_FF_MULTIBAND == 0) +SYS_UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq); +WORD32 rf_init(WORD32 t); + +// External function prototypes +UWORD8 Cust_is_band_high(UWORD16 radio_freq); +#endif + + +extern T_RF_BAND rf_band[]; +extern T_RF rf; + +/**************************************************************************/ +/**************************************************************************/ +/* DEFINITION OF MACROS FOR CHIPS SERIAL PROGRAMMATION */ +/**************************************************************************/ +/**************************************************************************/ + +/*------------------------------------------*/ +/* Is arfcn in the DCS band (512-885) ? */ +/*------------------------------------------*/ +#define IS_HIGH_BAND(arfcn) (((arfcn >= 512) && (arfcn <= 885)) ? 1 : 0) + + +/*------------------------------------------*/ +/* Send a value to LoCosto */ +/*------------------------------------------*/ +#define MOVE_REG_TSP_TO_RF(data, addr)\ + {\ + *TP_Ptr++ = TPU_MOVE(OCP_DATA_MSB, ((data)>>8) & 0x00FF); \ + *TP_Ptr++ = TPU_MOVE(OCP_DATA_LSB, (data) & 0x00FF); \ + *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_MSB, ((addr)>>8) & 0x00FF); \ + *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_LSB, (addr) & 0x00FF); \ + *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_START, 0x0001); \ + } + +/* RFTime environment */ +#if defined (HOST_TEST) + #include "hostmacros.h" +#endif + +/*------------------------------------------*/ +/* Trace arfcn for conversion debug */ +/*------------------------------------------*/ +#ifdef ARFCN_DEBUG + // ----Debug information : record all arfcn programmed into synthesizer! + #define MAX_ARFCN_TRACE 4096 // enough for 5 sessions of 124+374 + SYS_UWORD16 arfcn_trace[MAX_ARFCN_TRACE]; + static UWORD32 arfcn_trace_index = 0; + + void trace_arfcn(SYS_UWORD16 arfcn) + { + arfcn_trace[arfcn_trace_index++] = arfcn; + + // Wrap to beginning + if (arfcn_trace_index == MAX_ARFCN_TRACE) + arfcn_trace_index = 0; + } +#endif + + +/**************************************************************************/ +/**************************************************************************/ +/* DEFINITION OF HARWARE DEPENDANT CONSTANTS */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/* INTERNAL FUNCTIONS OF TPUDRV14.C */ +/* EFFECTIVE DOWNLOADING THROUGH TSP */ +/**************************************************************************/ +/**************************************************************************/ +// rx & tx +typedef struct tx_rx_s +{ + UWORD16 farfcn0; + WORD8 ou; +} +T_TX_RX; + +struct synth_s { + // common + UWORD16 arfcn0; + UWORD16 limit; + T_TX_RX tx_rx[2]; +}; + +struct rf_path_s { + UWORD8 rx_up; + UWORD8 rx_down; + UWORD8 tx_up; + UWORD8 tx_down; + struct synth_s *synth; +}; + +const struct synth_s synth_900[] = +{ + { 0, 124, {{ 890, 1}, { 935, 2}}},// gsm 0 - 124 + {974, 1023, {{ 880, 1}, { 925, 2}}},// egsm 975 - 1023 +}; + +const struct synth_s synth_1800[] = +{ + {511, 885, {{1710, 1}, {1805, 1}}}, // dcs 512 - 885 +}; + +const struct synth_s synth_1900[] = +{ + {511, 810, {{1850, 1}, {1930, 1}}}, // pcs 512 - 810; +}; + +const struct synth_s synth_850[] = +{ + {127, 192, {{ 824, 2}, { 869, 2}}}, // gsm850 128 - 251 //low + {127, 251, {{ 824, 1}, { 869, 2}}}, // gsm850 128 - 251 //high +}; + +#if RF_BAND_SYSTEM_INDEX == RF_QUADBAND +struct rf_path_s rf_path[] = { //same index used as for band_config[] - 1 + { RU_900, RD_900, TU_900, TD_900, (struct synth_s *)synth_900 }, //EGSM + { RU_1800, RD_1800, TU_1800, TD_1800, (struct synth_s *)synth_1800}, //DCS + { RU_1900, RD_1900, TU_1900, TD_1900, (struct synth_s *)synth_1900}, //PCS + { RU_850, RD_850, TU_850, TD_850, (struct synth_s *)synth_850 }, //GSM850 +}; +#endif + +#if RF_BAND_SYSTEM_INDEX == RF_EU_TRIBAND +struct rf_path_s rf_path[] = { //same index used as for band_config[] - 1 + { RU_850, RD_850, TU_900, TD_900, (struct synth_s *)synth_900 }, //EGSM + { RU_1800, RD_1800, TU_1800, TD_1800, (struct synth_s *)synth_1800}, //DCS + { RU_1900, RD_1900, TU_1900, TD_1900, (struct synth_s *)synth_1900}, //PCS + { RU_850, RD_850, TU_850, TD_850, (struct synth_s *)synth_850 }, //GSM850 +}; +#endif + +#if RF_BAND_SYSTEM_INDEX == RF_US_DUALBAND +struct rf_path_s rf_path[] = { //same index used as for band_config[] - 1 + { RU_900, RD_900, TU_900, TD_900, (struct synth_s *)synth_900 }, //EGSM + { RU_1800, RD_1800, TU_1800, TD_1800, (struct synth_s *)synth_1800}, //DCS + { RU_1800, RD_1800, TU_1900, TD_1900, (struct synth_s *)synth_1900}, //PCS + { RU_850, RD_850, TU_850, TD_850, (struct synth_s *)synth_850 }, //GSM850 +}; +#endif + +#if RF_BAND_SYSTEM_INDEX == RF_PCS1900_900_DUALBAND +struct rf_path_s rf_path[] = { //same index used as for band_config[] - 1 + { RU_850, RD_850, TU_900, TD_900, (struct synth_s *)synth_900 }, //EGSM + { RU_1800, RD_1800, TU_1800, TD_1800, (struct synth_s *)synth_1800}, //DCS + { RU_1800, RD_1800, TU_1900, TD_1900, (struct synth_s *)synth_1900}, //PCS + { RU_850, RD_850, TU_850, TD_850, (struct synth_s *)synth_850 }, //GSM850 +}; +#endif + + +UWORD32 calc_rf_freq(UWORD16 arfcn, UWORD8 downlink) +{ +UWORD32 farfcn; +struct synth_s *s; + + s = rf_path[rf_index].synth; + while(s->limit < arfcn) + s++; + + // Convert the ARFCN to the channel frequency (times 5 to avoid the decimal value) + farfcn = 5*s->tx_rx[downlink].farfcn0 + (arfcn - s->arfcn0); + + // LoCosto DLO carrier frequency is programmed in 100kHz increments. + // Therefore RF_FREQ = (channel frequency * 10) = (farfcn * 2) + return ( 2*farfcn ); +} + +#if (L1_FF_MULTIBAND == 0) +/*------------------------------------------*/ +/* Convert_l1_radio_freq */ +/*------------------------------------------*/ +/* conversion of l1 radio_freq to */ +/* real channel number */ +/*------------------------------------------*/ +SYS_UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq) +{ + switch(l1_config.std.id) + { + case GSM: + case DCS1800: + case PCS1900: + case GSM850: + return (radio_freq); +//omaps00090550 break; + + case DUAL: + { + if (radio_freq < l1_config.std.first_radio_freq_band2) + // GSM band... + return(radio_freq); + else + // DCS band... + return (radio_freq - l1_config.std.first_radio_freq_band2 + 512); + } +//omaps00090550 break; + + case DUALEXT: + { + if (radio_freq < l1_config.std.first_radio_freq_band2) + // E-GSM band... + { + if(radio_freq <= 124) + // GSM part... + return(radio_freq); + if(radio_freq < 174) + // Extended part... + return (radio_freq - 125 + 975); + else + // Extended part, special case of ARFCN=0 + return(0); + } + else + { + // DCS band... + return (radio_freq - l1_config.std.first_radio_freq_band2 + 512); + } + } +// break; + + case GSM_E: + { + if(radio_freq <= 124) + // GSM part... + return(radio_freq); + else + if(radio_freq < 174) + // Extended part... + return (radio_freq - 125 + 975); + else + // Extended part, special case of ARFCN=0 + return(0); + } +//omaps00090550 break; + + case DUAL_US: + { + if (radio_freq < l1_config.std.first_radio_freq_band2) + { + return(radio_freq - l1_config.std.first_radio_freq + 128); + } + else + { + // PCS band... + return (radio_freq - l1_config.std.first_radio_freq_band2 + 512); + } + } +// break; + + default: // should never occur. + return(radio_freq); + } // end of switch +} +#else +static const UWORD8 rf_band_idx_to_locosto_idx[] = +{ +#if (GSM900_SUPPORTED == 1) + 0, +#endif +#if (GSM850_SUPPORTED == 1) + 3, +#endif +#if (DCS1800_SUPPORTED == 1) + 1, +#endif +#if (PCS1900_SUPPORTED == 1) + 2 +#endif +}; + +SYS_UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq) +{ + UWORD8 band_index; + return(rf_convert_l1freq_to_arfcn_rfband(rf_convert_rffreq_to_l1freq(radio_freq), + &band_index)); +} + +#endif + +/*------------------------------------------*/ +/* rf_init */ +/*------------------------------------------*/ +/* Initialization routine for PLL */ +/* Effective downloading through TSP */ +/*------------------------------------------*/ +WORD32 rf_init(WORD32 t) +{ +//UWORD16 temp=(UWORD16)( ((UWORD32)(&drp_srm_api->control.retiming))&0xFFFF) ; + // enable control of retiming + MOVE_REG_TSP_TO_RF(RETIM_DISABLE, ((UWORD16)( ((UWORD32)(&drp_srm_api->control.retiming))&0xFFFF))); + + // Power ON the regulators by sending REG_ON script + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_REG_ON), ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))))); + + return(t); +} + + + + +#if (L1_FF_MULTIBAND == 0) +UWORD8 arfcn_to_rf_index(SYS_UWORD16 arfcn) +{ + UWORD8 index; + extern const T_STD_CONFIG std_config[]; + index = std_config[l1_config.std.id].band[0]; + + if ((std_config[l1_config.std.id].band[1] != BAND_NONE) && IS_HIGH_BAND(arfcn)) + index = std_config[l1_config.std.id].band[1]; + + return (index - 1); +} +#endif + +/*------------------------------------------*/ +/* rf_program */ +/*------------------------------------------*/ +/* Programs the RF synthesizer */ +/* called each frame */ +/* downloads NA counter value */ +/* t = start time in the current frame */ +/*------------------------------------------*/ //change 2 UWORD8 +UWORD32 rf_program(UWORD32 t, SYS_UWORD16 radio_freq, UWORD32 rx) +{ + UWORD32 rfdiv; + SYS_UWORD16 arfcn; + + #ifdef ARFCN_DEBUG + trace_arfcn(arfcn); + #endif + +#if (L1_FF_MULTIBAND == 0) + arfcn = Convert_l1_radio_freq(radio_freq); + + rf_index = arfcn_to_rf_index(arfcn); + + if (rf_index == 4) + { + rf_index = 0; + } + + +#else +{ + UWORD8 rf_band_index; +// rf_index = rf_band_idx_to_locosto_idx[rf_convert_l1freq_to_rf_band_idx(radio_freq)]; + arfcn=rf_convert_rffreq_to_l1freq_rfband(radio_freq, &rf_band_index); + rf_index = rf_band_idx_to_locosto_idx[rf_subband2band[rf_band_index]]; + arfcn=rf_convert_l1freq_to_arfcn_rfband(arfcn, &rf_band_index); +} +#endif + rfdiv = calc_rf_freq(arfcn, rx); + + MOVE_REG_TSP_TO_RF(rfdiv,((UWORD16)( ((UWORD32)(&drp_regs->RF_FREQL))&0xFFFF))); + + return(t); +} + +/*------------------------------------------*/ +/* rf_init_light */ +/*------------------------------------------*/ +/* Initialization routine for PLL */ +/* Effective downloading through TSP */ +/*------------------------------------------*/ +WORD32 rf_init_light(WORD32 t) +{ + // initialization for change of multi-band configuration dependent on STD + return(t); +} + + +/**************************************************************************/ +/**************************************************************************/ +/* EXTERNAL FUNCTIONS CALLED BY LAYER1 */ +/* COMMON TO L1 and TOOLKIT */ +/**************************************************************************/ +/**************************************************************************/ + +void l1dmacro_afc (SYS_UWORD16 afc_value, UWORD8 win_id) +{ + MOVE_REG_TSP_TO_RF(afc_value, ((UWORD16)( ((UWORD32)(&drp_srm_api->inout.afc.input.mem_xtal))&0xFFFF))); + + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_AFC), ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); +} + + +#define L1_NEW_ROC_ENABLE_FLAG (1) + + +#if (L1_NEW_ROC_ENABLE_FLAG == 1) + +/*------------------------------------------*/ +/* cust_get_if_dco_ctl_algo */ +/*------------------------------------------*/ +/* Defines which IF and DCO */ +/* algorythms are used */ +/* */ +/* */ +/*------------------------------------------*/ +/* NOTE: In the below code + * At high power levels, IF_100KHZ_DSP-> DRP->LIF_100KHZ and DSP->DCO_IF_100KHZ/DCO_IF_0_100KHZ + * low power levels IF_120KHZ_DSP-> DRP->LIF_120KHZ + HPF filter and DSP->DCO_NONE/DCO_IF_0KHZ */ + +void cust_get_if_dco_ctl_algo(UWORD16 *dco_algo_ctl, UWORD8 *if_ctrl, + UWORD8 input_level_flag, UWORD8 input_level, UWORD16 radio_freq, + UWORD8 if_threshold) +{ +#if (L1_FF_MULTIBAND == 0) + SYS_UWORD16 arfcn; +#else + UWORD16 rffreq; +#endif + + if ((!input_level_flag) || (input_level < if_threshold)) + { + *if_ctrl = IF_100KHZ_DSP; + *dco_algo_ctl = DCO_IF_100KHZ; + } + else + { + *if_ctrl = IF_120KHZ_DSP; + *dco_algo_ctl = DCO_NONE; + } +#if (L1_FF_MULTIBAND == 0) + arfcn = Convert_l1_radio_freq(radio_freq); + + switch(l1_config.std.id) + { + case GSM: + case GSM_E: + { + if ((arfcn == 5) || (arfcn == 70)) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } + break; + } + case DCS1800: + { + if ((arfcn == 521) || (arfcn == 586) || (arfcn == 651) || (arfcn == 716) ||(arfcn == 781) || (arfcn == 846)) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } + break; + } + case PCS1900: + { + if ((arfcn == 546) || (arfcn == 611) ||(arfcn == 676) || (arfcn == 741) ||(arfcn == 806) ) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } + break; + } + case GSM850: + { + if ((arfcn == 137) || (arfcn == 202)) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } + break; + } + case DUAL: + case DUALEXT: + { + if (radio_freq < l1_config.std.first_radio_freq_band2) + { + // GSM band... + if ((arfcn == 5) ||(arfcn == 70)) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } + } + else + // DCS band... + { + if ((arfcn == 521) || (arfcn == 586) || (arfcn == 651) || (arfcn == 716) ||(arfcn == 781) || (arfcn == 846)) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } + } + break; + } + case DUAL_US: + { + if (radio_freq < l1_config.std.first_radio_freq_band2) + { + // GSM 850 + if ((arfcn == 137) || (arfcn == 202)) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } + } + else + { + // PCS band... + if ((arfcn == 546) || (arfcn == 611) ||(arfcn == 676) || (arfcn == 741) ||(arfcn == 806) ) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } + } + break; + } + default: + break;// should never occur. + } // end of switch +#else //#if (L1_FF_MULTIBAND == 0) + //rffreq = rf_convert_l1freq_to_rffreq(radio_freq); + rffreq=radio_freq; // The argument passed to this function is the radio_freq and not l1_freq + if( +#if (GSM850_SUPPORTED == 1) + (137 == rffreq)||(202 == rffreq) || +#endif +#if (GSM900_SUPPORTED == 1) + (5 == rffreq)||(70 == rffreq) || +#endif +#if (DCS1800_SUPPORTED == 1) + (521 == rffreq)||(586 == rffreq) ||(651 == rffreq)||(716 == rffreq) ||(781 == rffreq)||(846 == rffreq) || +#endif +#if (PCS1900_SUPPORTED == 1) + (546+512 == rffreq) ||(611+512 == rffreq)||(676+512 == rffreq) ||(741+512 == rffreq)||(806+512 == rffreq) || +#endif + 0) + { + if (*if_ctrl == IF_100KHZ_DSP) + *dco_algo_ctl = DCO_IF_0KHZ_100KHZ; + else + *dco_algo_ctl = DCO_IF_0KHZ; + } +#endif // if (L1_FF_MULTIBAND == 0) +} +#else + +/*------------------------------------------*/ +/* cust_get_if_dco_ctl_algo */ +/*------------------------------------------*/ +/* Defines which IF and DCO */ +/* algorythms are used */ +/* */ +/* */ +/*------------------------------------------*/ + +/* NOTE: Below is the Old DCO algorithm in which ROC compensation was not enabled on DSP side + * To use this algorithm we need an appropriate DRP script which functions as below. + * IF_100KHZ_DSP-> DRP-ZIF and DSP-DCO_ZIF + * IF_120KHZ_DSP-> DRP_LIF_120KHZ + HPF filter and DSP-DCO_ZIF/DCO_NONE */ +void cust_get_if_dco_ctl_algo(UWORD16 *dco_algo_ctl, UWORD8 *if_ctrl, UWORD8 input_level_flag, UWORD8 input_level, UWORD16 radio_freq, UWORD8 if_threshold) +{ +#if (L1_FF_MULTIBAND == 0) + SYS_UWORD16 arfcn; +#else + UWORD16 rffreq; +#endif + + if ((!input_level_flag) | (input_level < if_threshold)) + { + *if_ctrl = IF_100KHZ_DSP; + *dco_algo_ctl = DCO_IF_0KHZ; + } + else{ + *if_ctrl = IF_120KHZ_DSP; + + + + //*dco_algo_ctl = DCO_IF_100KHZ; + *dco_algo_ctl = DCO_NONE; +#if (L1_FF_MULTIBAND == 0) + + arfcn = Convert_l1_radio_freq(radio_freq); + + switch(l1_config.std.id) + { + case GSM: + case GSM_E: + if ((arfcn == 5) |(arfcn == 70)) + + *dco_algo_ctl = DCO_IF_0KHZ; + break; + + case DCS1800: + if ((arfcn == 521) | (arfcn == 586) | (arfcn == 651) | (arfcn == 716) |(arfcn == 781) | (arfcn == 846)) + + *dco_algo_ctl = DCO_IF_0KHZ; + break; + + case PCS1900: + if ((arfcn == 546) | (arfcn == 611) |(arfcn == 676) | (arfcn == 741) |(arfcn == 806) ) + + *dco_algo_ctl = DCO_IF_0KHZ; + break; + + case GSM850: + if ((arfcn == 137) | (arfcn == 202)) + + *dco_algo_ctl = DCO_IF_0KHZ; + break; + + case DUAL: + case DUALEXT: + { + if (radio_freq < l1_config.std.first_radio_freq_band2) + { + // GSM band... + if ((arfcn == 5) |(arfcn == 70)) + + *dco_algo_ctl = DCO_IF_0KHZ; + } + else + // DCS band... + { + if ((arfcn == 521) | (arfcn == 586) | (arfcn == 651) | (arfcn == 716) |(arfcn == 781) | (arfcn == 846)) + + *dco_algo_ctl = DCO_IF_0KHZ; + } + } + break; + + case DUAL_US: + { + if (radio_freq < l1_config.std.first_radio_freq_band2) + { + // GSM 850 + if ((arfcn == 137) | (arfcn == 202)) + + *dco_algo_ctl = DCO_IF_0KHZ; + } + else + { + // PCS band... + if ((arfcn == 546) | (arfcn == 611) |(arfcn == 676) | (arfcn == 741) |(arfcn == 806) ) + + *dco_algo_ctl = DCO_IF_0KHZ; + } + } + break; + + default: + break;// should never occur. + } // end of switch +#else + rffreq = rf_convert_l1freq_to_rffreq(radio_freq); + if( +#if (GSM850_SUPPORTED == 1) + (137 == rffreq)||(202 == rffreq) || +#endif +#if (GSM900_SUPPORTED == 1) + (5 == rffreq)||(70 == rffreq) || +#endif +#if (DCS1800_SUPPORTED == 1) + (521 == rffreq)||(586 == rffreq) ||(651 == rffreq)||(716 == rffreq) ||(781 == rffreq)||(846 == rffreq) || +#endif +#if (PCS1900_SUPPORTED == 1) + (546+512 == rffreq) ||(611+512 == rffreq)||(676+512 == rffreq) ||(741+512 == rffreq)||(806+512 == rffreq) || +#endif + 0) + { + *dco_algo_ctl = DCO_IF_0KHZ; + } +#endif + } +} + +#endif +/*------------------------------------------*/ +/* agc */ +/*------------------------------------------*/ +/* Program a gain into IF amp */ +/* agc_value : gain in dB */ +/* */ +/* additional parameter for LNA setting */ +/*------------------------------------------*/ + +void l1dmacro_agc(SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna_off, UWORD8 if_ctl) +{ + signed int index; + WORD16 afe; + UWORD16 corner_freq = SCF_270KHZ ; //Corner frequency given in kHz + UWORD16 gain_comp = GAIN_COMP_ENABLE; //gain compensation scheme + UWORD16 if_setting; + UWORD16 lna_setting; + + UWORD16 arfcn ; + + + index = gain; + + // below is inserted to prevent wraparound of gain index in testmode + if (index >= AGC_TABLE_SIZE) + index = AGC_TABLE_SIZE-1; + if (index <= MIN_AGC_INDEX) + index = MIN_AGC_INDEX; + + if(lna_off) + afe = AFE_LOW_GAIN; + else + afe = AFE_HIGH_GAIN; + + if(if_ctl == IF_120KHZ_DSP) + if_setting = IF_120KHZ_DRP; + else + if_setting = IF_100KHZ_DRP; + + +#if (L1_FF_MULTIBAND == 0) + //LNA Changes + arfcn = Convert_l1_radio_freq(radio_freq); + //band_system_index = (UWORD16) convert_arfcn_to_band(arfcn); + lna_setting = (UWORD16) drp_generate_dbbif_setting_arfcn( (UWORD16) RF_BAND_SYSTEM_INDEX, arfcn); + //End LNA +#else +#if 0 + rf_band_idx = rf_convert_l1freq_to_rf_band_idx(radio_freq); + switch(rf_band_idx) + { +#if(GSM850_SUPPORTED) + case RF_GSM850: + drp_band_index = 0; + break; +#endif +#if(DCS1800_SUPPORTED) + case RF_DCS1800: + drp_band_index = 2; + break; +#endif +#if(PCS1900_SUPPORTED) + case RF_PCS1900: + drp_band_index = 3; + break; +#endif + default: + drp_band_index = 1; + break; + } +#endif // if 0 + + lna_setting = (UWORD16) drp_generate_dbbif_setting_arfcn( (UWORD16) RF_BAND_SYSTEM_INDEX, radio_freq); +#endif + //if_setting = IF_100KHZ_DRP; + // r2: implement the register rx_in for setting the configuration of the RX path + *TP_Ptr++ = TPU_AT(TRF_R2); + MOVE_REG_TSP_TO_RF(( (lna_setting <<8) | (corner_freq<<7) | (afe<<6) | (AGC_TABLE[index]<<2) | (gain_comp<<1) | (if_setting)), ((UWORD16)( ((UWORD32)(&drp_srm_api->inout.rx.rxon_input))&0xFFFF))); + +} + +/*------------------------------------------*/ +/* l1dmacro_rx_synth */ +/*------------------------------------------*/ +/* programs RF synth for recceive */ +/*------------------------------------------*/ +void l1dmacro_rx_synth(SYS_UWORD16 radio_freq) +{ + UWORD32 t; + + // Important: always use rx_synth_start_time for first TPU_AT + // Never remove below 2 lines!!! + t = l1_config.params.rx_synth_start_time; + *TP_Ptr++ = TPU_FAT (t); + + t = rf_program(t, radio_freq, 1); // direction is set to 1 for Rx +} + +/*------------------------------------------*/ +/* l1dmacro_tx_synth */ +/*------------------------------------------*/ +/* programs RF synth for transmit */ +/* programs OPLL for transmit */ +/*------------------------------------------*/ +void l1dmacro_tx_synth(SYS_UWORD16 radio_freq) +{ + UWORD32 t; + + // Important: always use tx_synth_start_time for first TPU_AT + // Never remove below 2 lines!!! + t = l1_config.params.tx_synth_start_time; + *TP_Ptr++ = TPU_FAT (t); + + t = rf_program(t, radio_freq, 0); // direction set to 0 for Tx +} + +/*------------------------------------------*/ +/* l1dmacro_rx_up */ +/*------------------------------------------*/ +/* Open window for normal burst reception */ +/*------------------------------------------*/ +#if (L1_RF_KBD_FIX == 1) +#if (L1_MADC_ON == 0) +void l1dmacro_rx_up (UWORD8 csf_filter_choice, UWORD8 kbd_config + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + UWORD8 kbd_tspact_config =0; + + if (kbd_config == KBD_DISABLED) + kbd_tspact_config = KBD_DIS_TSPACT; + + // r3: power ON RX + *TP_Ptr++ = TPU_AT(TRF_R3); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_RX_ON), ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))))); + + // r3_1: disable keyboard + *TP_Ptr++ = TPU_AT(TRF_R3_1); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config); + + // r4: enable TXM in Rx mode + *TP_Ptr++ = TPU_AT(TRF_R4); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].rx_up); + + // Program CSF filter appropriately + if(csf_filter_choice == L1_SAIC_HARDWARE_FILTER) + { + MOVE_REG_TSP_TO_RF(CSF_CWL_HARDWARE_FILTER_64TAP, (UWORD16)(&drp_regs->CSF_CWL)); + } + else + { + MOVE_REG_TSP_TO_RF(CSF_CWL_PROGRAMMABLE_FILTER_64TAP, (UWORD16)(&drp_regs->CSF_CWL)); + } + + // r5: enable RX_START + #if (L1_SAIC != 0)//Because for 0/2 interpolation, SAIC needs 1 additional symbol compared to legacy modem. + + #if (NEW_SNR_THRESHOLD==1) + if(saic_flag_rx_up==1) + { + #endif + + #if (ONE_THIRD_INTRPOL == 1) + *TP_Ptr++ = TPU_AT(TRF_R5-5); + #else + *TP_Ptr++ = TPU_AT(TRF_R5-4); + #endif + + #if (NEW_SNR_THRESHOLD==1) + } + else + { + *TP_Ptr++ = TPU_AT(TRF_R5); + } + #endif + + #else + *TP_Ptr++ = TPU_AT(TRF_R5); + #endif + + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | RX_START); + +} +#endif + + +#if (L1_MADC_ON == 1) +void l1dmacro_rx_up(UWORD8 adc_active, UWORD8 csf_filter_choice, UWORD8 kbd_config + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + UWORD8 kbd_tspact_config =0; + + if (kbd_config == KBD_DISABLED) + kbd_tspact_config = KBD_DIS_TSPACT; + + // r3: power ON RX + *TP_Ptr++ = TPU_AT(TRF_R3); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_RX_ON), (UWORD32)(&drp_regs->SCRIPT_STARTL)); + + if (adc_active == ACTIVE) + { + *TP_Ptr++ = TPU_AT(TRF_R8); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC|TXM_SLEEP); + *TP_Ptr++ = TPU_WAIT (2); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,TXM_SLEEP); + } + + // r3_1: disable keyboard + *TP_Ptr++ = TPU_AT(TRF_R3_1); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config); + + // r4: enable TXM in Rx mode + *TP_Ptr++ = TPU_AT(TRF_R4); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].rx_up); + + // Program CSF filter appropriately + if(csf_filter_choice == L1_SAIC_HARDWARE_FILTER) + { + MOVE_REG_TSP_TO_RF(CSF_CWL_HARDWARE_FILTER_64TAP, (UWORD32)(&drp_regs->CSF_CWL)); + } + else + { + MOVE_REG_TSP_TO_RF(CSF_CWL_PROGRAMMABLE_FILTER_64TAP, (UWORD32)(&drp_regs->CSF_CWL)); + } + // r5: enable RX_START + // Remember that between TRF_R5 and TRF_R4 there should be a buffer of around 4 qbits + #if (L1_SAIC != 0)//Because for 0/2 interpolation, SAIC needs 1 additional symbol compared to legacy modem. + + #if (NEW_SNR_THRESHOLD==1) + if(saic_flag_rx_up==1) + { + #endif + + #if (ONE_THIRD_INTRPOL == 1) + *TP_Ptr++ = TPU_AT(TRF_R5-5); + #else + *TP_Ptr++ = TPU_AT(TRF_R5-4); + #endif + + #if (NEW_SNR_THRESHOLD==1) + } + else + { + *TP_Ptr++ = TPU_AT(TRF_R5); + } + #endif + + #else + *TP_Ptr++ = TPU_AT(TRF_R5); + #endif + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | RX_START); + +} +#endif + +#endif /* (L1_RF_KBD_FIX == 1) */ + +#if (L1_RF_KBD_FIX == 0) +#if (L1_MADC_ON == 0) +void l1dmacro_rx_up (UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + + // r3: power ON RX + *TP_Ptr++ = TPU_AT(TRF_R3); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_RX_ON), (UWORD16)(&drp_regs->SCRIPT_STARTL)); + + // r4: enable TXM in Rx mode + *TP_Ptr++ = TPU_AT(TRF_R4); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].rx_up); + + // Program CSF filter appropriately + if(csf_filter_choice == L1_SAIC_HARDWARE_FILTER) + { + MOVE_REG_TSP_TO_RF(CSF_CWL_HARDWARE_FILTER_64TAP, (UWORD16)(&drp_regs->CSF_CWL)); + } + else + { + MOVE_REG_TSP_TO_RF(CSF_CWL_PROGRAMMABLE_FILTER_64TAP, (UWORD16)(&drp_regs->CSF_CWL)); + } + + // r5: enable RX_START + #if (L1_SAIC != 0)//Because for 0/2 interpolation, SAIC needs 1 additional symbol compared to legacy modem. + + #if (NEW_SNR_THRESHOLD==1) + if(saic_flag_rx_up==1) + { + #endif + + #if (ONE_THIRD_INTRPOL == 1) + *TP_Ptr++ = TPU_AT(TRF_R5-5); + #else + *TP_Ptr++ = TPU_AT(TRF_R5-4); + #endif + + #if (NEW_SNR_THRESHOLD==1) + } + else + { + *TP_Ptr++ = TPU_AT(TRF_R5); + } + #endif + + #else + *TP_Ptr++ = TPU_AT(TRF_R5); + #endif + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, RX_START); + +} +#endif + + +#if (L1_MADC_ON == 1) +void l1dmacro_rx_up(UWORD8 adc_active, UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + // r3: power ON RX + *TP_Ptr++ = TPU_AT(TRF_R3); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_RX_ON), (UWORD16)(&drp_regs->SCRIPT_STARTL)); + + if (adc_active == ACTIVE) + { + *TP_Ptr++ = TPU_AT(TRF_R8); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC); + *TP_Ptr++ = TPU_WAIT (2); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,0); + } + + + // r4: enable TXM in Rx mode + *TP_Ptr++ = TPU_AT(TRF_R4); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].rx_up); + + // Program CSF filter appropriately + if(csf_filter_choice == L1_SAIC_HARDWARE_FILTER) + { + MOVE_REG_TSP_TO_RF(CSF_CWL_HARDWARE_FILTER_64TAP, (UWORD16)(&drp_regs->CSF_CWL)); + } + else + { + MOVE_REG_TSP_TO_RF(CSF_CWL_PROGRAMMABLE_FILTER_64TAP, (UWORD16)(&drp_regs->CSF_CWL)); + } + + // r5: enable RX_START + #if (L1_SAIC != 0)//Because for 0/2 interpolation, SAIC needs 1 additional symbol compared to legacy modem. + + #if (NEW_SNR_THRESHOLD==1) + if(saic_flag_rx_up==1) + { + #endif + + #if (ONE_THIRD_INTRPOL == 1) + *TP_Ptr++ = TPU_AT(TRF_R5-5); + #else + *TP_Ptr++ = TPU_AT(TRF_R5-4); + #endif + + #if (NEW_SNR_THRESHOLD==1) + } + else + { + *TP_Ptr++ = TPU_AT(TRF_R5); + } + #endif + + #else + *TP_Ptr++ = TPU_AT(TRF_R5); + #endif + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, RX_START); + +} +#endif +#endif /* (L1_RF_KBD_FIX == 0) */ + + +/*------------------------------------------*/ +/* l1pdmacro_rx_down */ +/*------------------------------------------*/ +/* Close window for normal burst reception */ +/*------------------------------------------*/ +void l1dmacro_rx_down (WORD32 t) +{ + + //r6: Disable ROC script + *TP_Ptr++ = TPU_FAT(t + TRF_R6); + MOVE_REG_TSP_TO_RF((DRP_ROC), ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); + + + + //r7: Disable Rx_Start & Disable RF switch & send Idle script + *TP_Ptr++ = TPU_FAT(t + TRF_R7); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].rx_down); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, 0); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_IDLE),((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); + +} + +/*------------------------------------------*/ +/* l1dmacro_tx_up */ +/*------------------------------------------*/ +/* Open transmission window for normal burst*/ +/*------------------------------------------*/ +#if (L1_RF_KBD_FIX == 1) +void l1dmacro_tx_up (UWORD8 kbd_config) +{ + UWORD8 kbd_tspact_config =0; + + if (kbd_config == KBD_DISABLED) + kbd_tspact_config = KBD_DIS_TSPACT; + + // t2: Power ON TX + *TP_Ptr++ = TPU_AT(TRF_T2); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TX_ON), ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); + + // t3: put the TXM in RX mode + *TP_Ptr++ = TPU_AT(TRF_T3); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].tx_down); + + // t3_1: disable keyboard + *TP_Ptr++ = TPU_AT(TRF_T3_1); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config); + + // t4: enable the APC LDO + *TP_Ptr++ = TPU_AT(TRF_T4); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN); + + // t5: enable the APC module + *TP_Ptr++ = TPU_AT(TRF_T5); + //SG *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | APC_EN); + + // t6: enable TX start and enable of Vramp + //SG*TP_Ptr++ = TPU_AT(TRF_T6); + //SG *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | APC_EN | TX_START | START_APC); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | TX_START ); + + *TP_Ptr++ = TPU_AT(TRF_T6); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | APC_EN | TX_START ); + + *TP_Ptr++ = TPU_AT(TRF_T7); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | APC_EN | TX_START | START_APC); + + // t7: enable TX start and enable of Vramp - Internal mode + //*TP_Ptr++ = TPU_AT(TRF_T7); + //*TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | APC_EN | TX_START | START_APC ); + + // t7: enable TX start and enable of Vramp + //*TP_Ptr++ = TPU_AT(TRF_T7+4); + //*TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | APC_EN | TX_START ); + + // t8: enable the TXEN of the TXM + *TP_Ptr++ = TPU_AT(TRF_T8); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].tx_up); + + } + + #endif /*(L1_RF_KBD_FIX == 1)*/ + + #if (L1_RF_KBD_FIX == 0) + + void l1dmacro_tx_up (void) + { + + + + + + // t2: Power ON TX + *TP_Ptr++ = TPU_AT(TRF_T2); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TX_ON),((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); + + // t3: put the TXM in RX mode + *TP_Ptr++ = TPU_AT(TRF_T3); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].tx_down); + + + + + + // t4: enable the APC LDO + *TP_Ptr++ = TPU_AT(TRF_T4); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN); + + // t5: enable the APC module + *TP_Ptr++ = TPU_AT(TRF_T5); + //SG *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | APC_EN); + + // t6: enable TX start and enable of Vramp + //SG*TP_Ptr++ = TPU_AT(TRF_T6); + //SG *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | APC_EN | TX_START | START_APC); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | TX_START ); + + *TP_Ptr++ = TPU_AT(TRF_T6); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | APC_EN | TX_START ); + + *TP_Ptr++ = TPU_AT(TRF_T7); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | APC_EN | TX_START | START_APC); + + // t7: enable TX start and enable of Vramp - Internal mode + //*TP_Ptr++ = TPU_AT(TRF_T7); + //*TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | APC_EN | TX_START | START_APC ); + + // t7: enable TX start and enable of Vramp + //*TP_Ptr++ = TPU_AT(TRF_T7+4); + //*TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, LDO_EN | APC_EN | TX_START ); + + // t8: enable the TXEN of the TXM + *TP_Ptr++ = TPU_AT(TRF_T8); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].tx_up); + + } + +#endif /* (L1_RF_KBD_FIX == 0)*/ + +/*-------------------------------------------*/ +/* l1dmacro_tx_down */ +/*-------------------------------------------*/ +/* Close transmission window for normal burst*/ +/*-------------------------------------------*/ +#if (L1_RF_KBD_FIX == 1) +void l1dmacro_tx_down (WORD32 t, BOOL tx_flag, UWORD8 adc_active, UWORD8 kbd_config) +{ + UWORD8 kbd_tspact_config =0; + + if (kbd_config == KBD_DISABLED) + kbd_tspact_config = KBD_DIS_TSPACT; + + + if (adc_active == ACTIVE) { + // 36qbits = (10qbits for TPU programming) + (26qbits duration to convert the first ADC channel (= Battery)) + if ((t)<(TRF_T8+2-TRF_T9)) //Done to enable RACH Burst Support + { + l1dmacro_adc_read_tx (TRF_T8+10, rf_path[rf_index].tx_up); + } + else + { + l1dmacro_adc_read_tx (t + TRF_T9, rf_path[rf_index].tx_up); + } + } + + + + // t10: disable APC + *TP_Ptr++ = TPU_FAT (t + TRF_T10); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | APC_EN | TX_START ); + + // t11: disable PA + *TP_Ptr++ = TPU_FAT (t + TRF_T11); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].tx_down); + // disable Tx_Start + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | APC_EN ); + + // t12: power off Locosto: IDLE SCRIPT + *TP_Ptr++ = TPU_FAT (t + TRF_T12); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_IDLE), ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); + + // t13: Switch off APC + *TP_Ptr++ = TPU_FAT (t + TRF_T13); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, 0); + + } +#endif /*(L1_RF_KBD_FIX == 1)*/ + + + +#if (L1_RF_KBD_FIX == 0) +void l1dmacro_tx_down (WORD32 t, BOOL tx_flag, UWORD8 adc_active) +{ + + if (adc_active == ACTIVE) { + // 36qbits = (10qbits for TPU programming) + (26qbits duration to convert the first ADC channel (= Battery)) + l1dmacro_adc_read_tx (t + TRF_T9, rf_path[rf_index].tx_up); + } + + // t10: disable APC + *TP_Ptr++ = TPU_FAT (t + TRF_T10); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | APC_EN | TX_START ); + + // t11: disable PA + *TP_Ptr++ = TPU_FAT (t + TRF_T11); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, rf_path[rf_index].tx_down); + // disable Tx_Start + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, kbd_tspact_config | LDO_EN | APC_EN ); + + // t12: power off Locosto: IDLE SCRIPT + *TP_Ptr++ = TPU_FAT (t + TRF_T12); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_IDLE), (UWORD16)(&drp_regs->SCRIPT_STARTL)); + + // t13: Switch off APC + *TP_Ptr++ = TPU_FAT (t + TRF_T13); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, 0); + +} + + +#endif/*(L1_RF_KBD_FIX == 0)*/ + +/* + * l1dmacro_rx_nb + * + * Receive Normal burst + */ +#if (L1_RF_KBD_FIX == 1) + #if (L1_MADC_ON == 1) +void l1dmacro_rx_nb (SYS_UWORD16 radio_freq, UWORD8 adc_active, UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + l1dmacro_rx_up(adc_active, csf_filter_choice, L1_KBD_DIS_RX_NB + #if(NEW_SNR_THRESHOLD==1) + , saic_flag_rx_up + #endif + ); + l1dmacro_rx_down (STOP_RX_SNB); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_NB * (-TRF_R3_1 + STOP_RX_SNB - TRF_R7); +} +#else +void l1dmacro_rx_nb (SYS_UWORD16 radio_freq,UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + l1dmacro_rx_up(csf_filter_choice, L1_KBD_DIS_RX_NB + #if(NEW_SNR_THRESHOLD==1) + , saic_flag_rx_up + #endif + ); + l1dmacro_rx_down (STOP_RX_SNB); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_NB * (-TRF_R3_1 + STOP_RX_SNB - TRF_R7); +} +#endif +#endif /*(L1_RF_KBD_FIX == 1)*/ + +#if (L1_RF_KBD_FIX == 0) + #if (L1_MADC_ON == 1) +void l1dmacro_rx_nb (SYS_UWORD16 radio_freq, UWORD8 adc_active, UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + l1dmacro_rx_up(adc_active, csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , saic_flag_rx_up + #endif + ); + l1dmacro_rx_down (STOP_RX_SNB); + +} +#else +void l1dmacro_rx_nb (SYS_UWORD16 radio_freq,UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + l1dmacro_rx_up(csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , saic_flag_rx_up + #endif + ); + l1dmacro_rx_down (STOP_RX_SNB); + +} +#endif + +#endif/*(L1_RF_KBD_FIX == 0)*/ + + + +/* + * l1dmacro_rx_sb + * Receive Synchro burst +*/ +#if (L1_RF_KBD_FIX == 1) +#if (L1_MADC_ON == 1) +void l1dmacro_rx_sb (SYS_UWORD16 radio_freq,UWORD8 adc_active) +{ + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_SB + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + + l1dmacro_rx_down (STOP_RX_SB); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_SB * (-TRF_R3_1 + STOP_RX_SB - TRF_R7); +} + +#else +void l1dmacro_rx_sb (SYS_UWORD16 radio_freq) +{ + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_SB + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1dmacro_rx_down (STOP_RX_SB); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_SB * (-TRF_R3_1 + STOP_RX_SB - TRF_R7); +} +#endif + +#endif/*(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) +#if (L1_MADC_ON == 1) +void l1dmacro_rx_sb (SYS_UWORD16 radio_freq,UWORD8 adc_active) +{ + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1dmacro_rx_down (STOP_RX_SB); + +} + +#else +void l1dmacro_rx_sb (SYS_UWORD16 radio_freq) +{ + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1dmacro_rx_down (STOP_RX_SB); + +} +#endif + +#endif/*(L1_RF_KBD_FIX == 0)*/ + +/* + * l1dmacro_rx_ms + * + * Receive Power Measurement window + */ + #if(L1_RF_KBD_FIX == 1) + #if (L1_MADC_ON == 1) + void l1dmacro_rx_ms (SYS_UWORD16 radio_freq,UWORD8 adc_active) +{ + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_MS + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1dmacro_rx_down (STOP_RX_PW_1); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_MS * (-TRF_R3_1 + STOP_RX_PW_1 - TRF_R7); +} + + #else +void l1dmacro_rx_ms (SYS_UWORD16 radio_freq) +{ + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_MS + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1dmacro_rx_down (STOP_RX_PW_1); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_MS * (-TRF_R3_1 + STOP_RX_PW_1 - TRF_R7); +} +#endif +#endif/*(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) +#if (L1_MADC_ON == 1) + void l1dmacro_rx_ms (SYS_UWORD16 radio_freq,UWORD8 adc_active) +{ + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1dmacro_rx_down (STOP_RX_PW_1); + +} + + #else +void l1dmacro_rx_ms (SYS_UWORD16 radio_freq) +{ + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1dmacro_rx_down (STOP_RX_PW_1); + +} +#endif + +#endif/*(L1_RF_KBD_FIX == 0)*/ + +/* + * l1dmacro_rx_fb + * + * Receive Frequency burst + */ +#if(L1_RF_KBD_FIX == 1) +#if (L1_MADC_ON == 1) +void l1dmacro_rx_fb (SYS_UWORD16 radio_freq,UWORD8 adc_active) +#else +void l1dmacro_rx_fb (SYS_UWORD16 radio_freq) +#endif +{ +#if (L1_MADC_ON == 1) + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_FB + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); +#else + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_FB + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); +#endif + l1s.total_kbd_on_time = 5000; + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + + l1dmacro_rx_down (STOP_RX_FB); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_FB * (STOP_RX_FB - TRF_R7); +} +#endif/*(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) +#if (L1_MADC_ON == 1) +void l1dmacro_rx_fb (SYS_UWORD16 radio_freq,UWORD8 adc_active) +#else +void l1dmacro_rx_fb (SYS_UWORD16 radio_freq) +#endif +{ +#if (L1_MADC_ON == 1) + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); +#else + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); +#endif + + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + *TP_Ptr++ = TPU_AT(0); + + l1dmacro_rx_down (STOP_RX_FB); + +} + +#endif/*(L1_RF_KBD_FIX == 0)*/ + +/* + * l1dmacro_rx_fb26 + * + * Receive Frequency burst for TCH. + */ + #if(L1_RF_KBD_FIX == 1) + #if (L1_MADC_ON == 1) + void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq,UWORD8 adc_active) +{ + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_FB26 + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1s.total_kbd_on_time = 5000; + *TP_Ptr++ = TPU_AT(0); + + l1dmacro_rx_down (STOP_RX_FB26); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_FB26 * (STOP_RX_FB26 - TRF_R7); +} + + #else +void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq) +{ + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_FB26 + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + l1s.total_kbd_on_time = 5000; + *TP_Ptr++ = TPU_AT(0); + + l1dmacro_rx_down (STOP_RX_FB26); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_RX_FB26 * (STOP_RX_FB26 - TRF_R7); +} +#endif +#endif/*(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) +#if (L1_MADC_ON == 1) + void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq,UWORD8 adc_active) +{ + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + + *TP_Ptr++ = TPU_AT(0); + + l1dmacro_rx_down (STOP_RX_FB26); + +} + + #else +void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq) +{ + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); + + *TP_Ptr++ = TPU_AT(0); + + l1dmacro_rx_down (STOP_RX_FB26); + +} +#endif +#endif/*(L1_RF_KBD_FIX == 0)*/ + +/* + * l1dmacro_tx_nb + * + * Transmit Normal burst + */ +#if(L1_RF_KBD_FIX == 1) + + void l1dmacro_tx_nb (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active) +{ + l1dmacro_tx_up (L1_KBD_DIS_TX_NB); + l1dmacro_tx_down (l1_config.params.tx_nb_duration, FALSE, adc_active, L1_KBD_DIS_TX_NB); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_TX_NB * (-TRF_T3_1 + l1_config.params.tx_nb_duration + TRF_T12); +} + +#endif/*#if(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) + void l1dmacro_tx_nb (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active) +{ + l1dmacro_tx_up (); + l1dmacro_tx_down (l1_config.params.tx_nb_duration, FALSE, adc_active); + +} + +#endif/*#if(L1_RF_KBD_FIX == 0)*/ + +/* + * l1dmacro_tx_ra + * + * Transmit Random Access burst + */ +#if(L1_RF_KBD_FIX == 1) + +void l1dmacro_tx_ra (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active) +{ + l1dmacro_tx_up (L1_KBD_DIS_TX_RA); + l1dmacro_tx_down (l1_config.params.tx_ra_duration, FALSE, adc_active, L1_KBD_DIS_TX_RA); + l1s.total_kbd_on_time = l1s.total_kbd_on_time - L1_KBD_DIS_TX_RA * (-TRF_T3_1 + l1_config.params.tx_ra_duration + TRF_T12); +} +#endif /*#if(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) +void l1dmacro_tx_ra (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active) +{ + l1dmacro_tx_up (); + l1dmacro_tx_down (l1_config.params.tx_ra_duration, FALSE, adc_active); + +} +#endif/*#if(L1_RF_KBD_FIX == 0)*/ + + /* + * l1dmacro_rx_cont + * + * Receive continuously + */ +#if(L1_RF_KBD_FIX == 1) + #if (L1_MADC_ON == 1) + void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr, + UWORD8 adc_active, UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + l1dmacro_rx_up (adc_active, csf_filter_choice, KBD_DISABLED + #if(NEW_SNR_THRESHOLD==1) + , saic_flag_rx_up + #endif + ); +} + #else +void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr, + UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + l1dmacro_rx_up (csf_filter_choice,KBD_DISABLED + #if(NEW_SNR_THRESHOLD==1) + , saic_flag_rx_up + #endif + ); +} +#endif +#endif/*#if(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) + #if (L1_MADC_ON == 1) + void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr, + UWORD8 adc_active, UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + l1dmacro_rx_up (adc_active, csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , saic_flag_rx_up + #endif + ); +} + #else +void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr, + UWORD8 csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , UWORD8 saic_flag_rx_up + #endif + ) +{ + l1dmacro_rx_up (csf_filter_choice + #if(NEW_SNR_THRESHOLD==1) + , saic_flag_rx_up + #endif + ); +} +#endif + +#endif/*#if(L1_RF_KBD_FIX == 0)*/ + + + /* + * l1dmacro_tx_cont + * + * Transmit continuously + */ +#if(L1_RF_KBD_FIX == 1) +void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr) +{ + l1dmacro_tx_up (KBD_DISABLED); +} +#endif/*#if(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) +void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr) +{ + l1dmacro_tx_up (); +} +#endif/*#if(L1_RF_KBD_FIX == 0)*/ + + /* + * l1d_macro_stop_cont + * + * Stop continuous Tx or Rx + */ +#if(L1_RF_KBD_FIX == 1) +void l1dmacro_stop_cont (void) +{ + if (l1_config.tmode.rf_params.down_up == TMODE_DOWNLINK) + l1dmacro_rx_down(STOP_RX_SNB); + else + l1dmacro_tx_down(l1_config.params.tx_nb_duration, FALSE, 0, KBD_DISABLED); +} +#endif/*#if(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) +void l1dmacro_stop_cont (void) +{ + if (l1_config.tmode.rf_params.down_up == TMODE_DOWNLINK) + l1dmacro_rx_down(STOP_RX_SNB); + else + l1dmacro_tx_down(l1_config.params.tx_nb_duration, FALSE, 0); +} + +#endif/* */ + + +/*------------------------------------------*/ +/* l1dmacro_reset_hw */ +/*------------------------------------------*/ +/* Reset and set OFFSET register */ +/*------------------------------------------*/ + +void l1dmacro_reset_hw(UWORD32 servingCellOffset) +{ + TPU_Reset(1); // reset TPU only, no TSP reset + TPU_Reset(0); + TP_Ptr = (UWORD16 *) TPU_RAM; + + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, TXM_SLEEP); + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_L, TXM_SLEEP); + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_IDLE),((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); + + *TP_Ptr++ = TPU_OFFSET(servingCellOffset); + +} + +// l1dmacro_RF_sleep +// Program RF for BIG or DEEP sleep + + +void l1dmacro_RF_sleep (void) +{ + // sending REG_OFF script + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_REG_OFF), ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); + + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, TXM_SLEEP); //Shutdown FEM + + *TP_Ptr++ = TPU_SLEEP; + TP_Ptr = (SYS_UWORD16 *) TPU_RAM; + TP_Enable(1); + TPU_wait_idle(); + +} + + +// l1dmacro_RF_wakeup +//* wakeup RF from BIG or DEEP sleep + +void l1dmacro_RF_wakeup (void) +{ + // sending REG_ON script + MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_REG_ON), ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF))); + + *TP_Ptr++ = TPU_SLEEP; + TP_Ptr = (SYS_UWORD16 *) TPU_RAM; + TP_Enable(1); + TPU_wait_idle(); + + +} + + +// l1dmacro_init_hw +// Reset VEGA, then remove reset +// Init RF/IF synthesizers + +void l1dmacro_init_hw(void) +{ + WORD32 t = 100; // start time for actions + + TP_Reset(1); // reset TPU and TSP + + // GSM 1.5 : TPU clock enable is in TPU + //--------------------------------------- + TPU_ClkEnable(1); // TPU CLOCK ON + + TP_Reset(0); + + + TP_Ptr = (UWORD16 *) TPU_RAM; + + // Set FEM to inactive state before turning ON the RF Board + // At this point the RF regulators are still OFF. Thus the + // FEM command is not inverted yet => Must use the FEM "SLEEP programming" + + + // TPU_SLEEP + l1dmacro_idle(); + + *TP_Ptr++ = TPU_AT(t); + *TP_Ptr++ = TPU_SYNC(0); + + //Check Initialisation or Reset for TPU2OCP + + + *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U, TXM_SLEEP); + + t = 1000; // arbitrary start time + + t = rf_init(t); // Initialize RF Board + + *TP_Ptr++ = TPU_AT(t); + + // TPU_SLEEP + l1dmacro_idle(); + + return; +} + +/*------------------------------------------*/ +/* l1dmacro_init_hw_light */ +/*------------------------------------------*/ +/* Reset VEGA, then remove reset */ +/* Init RF/IF synthesizers */ +/*------------------------------------------*/ +void l1dmacro_init_hw_light(void) +{ + UWORD32 t = 100; // start time for actions // + TP_Ptr = (SYS_UWORD16 *) TPU_RAM; // + *TP_Ptr++ = TPU_AT(t); // + t = 1000; // arbitrary start time // + + t = rf_init_light(t); // Initialize RF Board // + + *TP_Ptr++ = TPU_AT(t); // + l1dmacro_idle(); // + + return; +} + +//BHO added +/* + * l1dmacro_rx_fbsb + * + * Receive Frequency burst + */ + +#if ((REL99 == 1) && (FF_BHO == 1)) +#if(L1_RF_KBD_FIX == 1) +#if (L1_MADC_ON == 1) +void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq, UWORD8 adc_active) +#else +void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq) +#endif +{ +#if (L1_MADC_ON == 1) + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_FB + #if(NEW_SNR_THRESHOLD==1) + , SAIC_OFF + #endif + ); +#else + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER, L1_KBD_DIS_RX_FB); +#endif + + + // same as rx_fb + *TP_Ptr++ = TPU_AT(0); // 1 + *TP_Ptr++ = TPU_AT(0); // 2 + *TP_Ptr++ = TPU_AT(0); // 3 + *TP_Ptr++ = TPU_AT(0); // 4 + *TP_Ptr++ = TPU_AT(0); // 5 + *TP_Ptr++ = TPU_AT(0); // 6 + *TP_Ptr++ = TPU_AT(0); // 7 + *TP_Ptr++ = TPU_AT(0); // 8 + *TP_Ptr++ = TPU_AT(0); // 9 + *TP_Ptr++ = TPU_AT(0); // 10 + *TP_Ptr++ = TPU_AT(0); // 11 + + // one more for SB + *TP_Ptr++ = TPU_AT(0); // 12 + + l1dmacro_rx_down (STOP_RX_FBSB); +} +#endif/*(L1_RF_KBD_FIX == 1)*/ + +#if(L1_RF_KBD_FIX == 0) +#if (L1_MADC_ON == 1) +void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq, UWORD8 adc_active) +#else +void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq) +#endif +{ +#if (L1_MADC_ON == 1) + l1dmacro_rx_up(adc_active, L1_SAIC_HARDWARE_FILTER); +#else + l1dmacro_rx_up(L1_SAIC_HARDWARE_FILTER); +#endif + + // same as rx_fb + *TP_Ptr++ = TPU_AT(0); // 1 + *TP_Ptr++ = TPU_AT(0); // 2 + *TP_Ptr++ = TPU_AT(0); // 3 + *TP_Ptr++ = TPU_AT(0); // 4 + *TP_Ptr++ = TPU_AT(0); // 5 + *TP_Ptr++ = TPU_AT(0); // 6 + *TP_Ptr++ = TPU_AT(0); // 7 + *TP_Ptr++ = TPU_AT(0); // 8 + *TP_Ptr++ = TPU_AT(0); // 9 + *TP_Ptr++ = TPU_AT(0); // 10 + *TP_Ptr++ = TPU_AT(0); // 11 + + // one more for SB + *TP_Ptr++ = TPU_AT(0); // 12 + + l1dmacro_rx_down (STOP_RX_FBSB); +} +#endif/*(L1_RF_KBD_FIX == 0)*/ +#endif // #if ((REL99 == 1) && (FF_BHO == 1)) + +////BHO
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/L1/tpudrv/tpudrv61.h Mon Aug 11 04:45:42 2014 +0000 @@ -0,0 +1,459 @@ +/****************** Revision Controle System Header *********************** + * GSM Layer 1 software + * Copyright (c) Texas Instruments 1998 + * + * Filename tpudrv61.h + * Version 1.0 + * Date June 1st, 2005 + * + ****************** Revision Controle System Header ***********************/ +//FLEXIBLE ADC... +#undef VARIABLE_ADC_ON_TX +//VARIABLE_ADC_ON_TX- represents the number of symbols before TRF_T11 (the time where the PA is disabled) +//the ADC conversion should be performed. VARIABLE_ADC_ON_TX- has a valid range from 14 to 155 symbols. +//Hence, to use the fix, VARIABLE_ADC_ON_TX- must be defined to a value between 14 and 155, compile time. +//This will cause the ADC conversion offset (TRF_T9) to be calculated by the following equation: +//TRF_T9 = TRF_T11-VARIABLE_ADC_ON_TX*4 +//The customer is expected to use a value of 76. If this compile flag is not set, the ADC conversion offset (TRF_T9) +// is set to a default value of 14 symbols before TXEN is disabled (i.e. the default timing is 40 qbit before the +// TX down time anchor and 20 qb before the last tail bit). +#define VARIABLE_ADC_ON_TX 76 + +#if(L1_RF_KBD_FIX == 1) +// Keyboard disable config: +#define L1_KBD_DIS_RX_NB 1 +#define L1_KBD_DIS_RX_SB 1 +#define L1_KBD_DIS_RX_FB 1 +#define L1_KBD_DIS_RX_FB26 1 +#define L1_KBD_DIS_RX_MS 1 +#define L1_KBD_DIS_TX_NB 1 +#define L1_KBD_DIS_TX_RA 1 + +#define KBD_DISABLED 1 + +#endif/*(L1_RF_KBD_FIX == 1)*/ + +//Fixed declaration of script numbers +#define DRP_REG_ON (0x0000) +#define DRP_TX_ON (0x0001) +#define DRP_RX_ON (0x0002) +#define DRP_TEMP_CONV (0x0003) +#define DRP_ROC (0x0004) +#define DRP_REG_OFF (0x0007) +#define DRP_AFC (0x000D) +#define DRP_IDLE (0x000F) + +#define SCRIPT_EN (0x3080) + +#define START_SCRIPT(script_nb) (SCRIPT_EN | script_nb) + +// IF settings +#define IF_100KHZ_DRP 0 +#define IF_120KHZ_DRP 1 + +// Gain Compensation Enable/Disable +#define GAIN_COMP_DISABLE (0x0) //Default +#define GAIN_COMP_ENABLE (0x1) + +// AFE Gains Definition +#define AFE_LOW_GAIN (0x0) // 11 dB +#define AFE_HIGH_GAIN (0x1) // 38 dB + +// ABE Gains Definition +#define ABE_0_DB (0x0) +#define ABE_2_DB (0x1) +#define ABE_5_DB (0x2) +#define ABE_8_DB (0x3) +#define ABE_11_DB (0x4) +#define ABE_14_DB (0x5) +#define ABE_17_DB (0x6) +#define ABE_20_DB (0x7) +#define ABE_23_DB (0x8) + +// Switched Cap Filter Corner Freq Defition +#define SCF_270KHZ 0 +#define SCF_400KHZ 1 + +// Retiming definition +#define RETIM_DISABLE (0x0000) +#define RETIM_TX_ONLY (0x0001) +#define RETIM_RX_ONLY (0x0002) +#define RETIM_FULL (0x0003) + +// IF settings for DSP +#define IF_100KHZ_DSP 2 +#define IF_120KHZ_DSP 1 + +// DCO algo settings +#define DCO_IF_100KHZ 1 +#define DCO_IF_0KHZ 2 +#define DCO_IF_0KHZ_100KHZ 3 +#define DCO_NONE 0 + + +//--- Configuration values +//- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0 + // This is also used in l1_rf14h to select the SWAP_IQ + + + //- Bit definitions for TST register programings, etc +#define BIT_0 0x000001 +#define BIT_1 0x000002 +#define BIT_2 0x000004 +#define BIT_3 0x000008 +#define BIT_4 0x000010 +#define BIT_5 0x000020 +#define BIT_6 0x000040 +#define BIT_7 0x000080 +#define BIT_8 0x000100 +#define BIT_9 0x000200 +#define BIT_10 0x000400 +#define BIT_11 0x000800 +#define BIT_12 0x001000 +#define BIT_13 0x002000 +#define BIT_14 0x004000 +#define BIT_15 0x008000 +#define BIT_16 0x010000 +#define BIT_17 0x020000 +#define BIT_18 0x040000 +#define BIT_19 0x080000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 + + +//- Base REGISTER definitions - + +//- RF signals connected to TSPACT - +#define RX_START BIT_0 // RX_START of DRP2 +#define TX_START BIT_1 // TX_START of DRP2 modulator +#define START_APC BIT_2 // Start of the APC module +#define LDO_EN BIT_3 // Activation of the internal LDO inside the APC bloc +#if(L1_RF_KBD_FIX == 1) +#define KBD_DIS_TSPACT BIT_4 // Disable keyboard +#endif +#define APC_EN BIT_5 // Enable of the APC module +#define START_ADC BIT_0 // Activation of the Triton ADC +#define B3 BIT_3 // Control of the RFMD TX module +#define B1 BIT_5 // Control of the RFMD TX module +#define TX_EN BIT_6 // Control of the RFMD TX module +#define B2 BIT_7 // Control of the RFMD TX module + +#define TXM_SLEEP (0) // To avoid leakage during Deep-Seep + +// DRP write register +#define OCP_DATA_MSB 0x05 +#define OCP_DATA_LSB 0x04 +#define OCP_ADDRESS_MSB 0x0B +#define OCP_ADDRESS_LSB 0x0A +#define OCP_ADDRESS_START 0x01 + +// TSPACT +#define REG_SPI_ACT_U 0x07 +#define REG_SPI_ACT_L 0x06 + +// 3-band config +// RX_UP/DOWN and TX_UP/DOWN +#define RU_900 ( B1 | B3 ) +#define RD_900 ( B1 | B3 ) +#define TU_900 ( TX_EN | B1 | B3 ) +#define TD_900 ( B1 | B3 ) + +#define RU_850 ( B3 ) +#define RD_850 ( B3 ) +#define TU_850 ( TX_EN | B3 ) +#define TD_850 ( B3 ) + +#define RU_1800 ( B2 | B3 ) +#define RD_1800 ( B2 | B3 ) +#define TU_1800 ( TX_EN | B1 | B2 | B3 ) +#define TD_1800 ( B2 | B3 ) + + +#define RU_1900 ( B1 | B2 | B3 ) +#define RD_1900 ( B1 | B2 | B3 ) +#define TU_1900 ( TX_EN | B1 | B2 | B3 ) +#define TD_1900 ( B1 | B2 | B3 ) + + + + +//--- TIMINGS ---------------------------------------------------------- + +/*------------------------------------------*/ +/* Download delay values */ +/*------------------------------------------*/ +// 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12) + +#define T TPU_CLOCK_RANGE + + +// - TPU instruction into TSP timings --- +// 1 tpu instruction = 1 qbit +#define DLT_1 1 // 1 tpu instruction = 1 qbit +#define DLT_2 2 // 2 tpu instruction = 2 qbit +#define DLT_3 3 // 3 tpu instruction = 3 qbit +#define DLT_4 4 // 4 tpu instruction = 4 qbit + +// - TPU command execution + serialization length --- +#define DLT_4B 5 // 5*move + + +// - INIT (delta or DLT) timings --- +#define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON +#define DLT_I2 200 // Regulators turn on time +#define DLT_I3 5 // Time required to set RF_SER_ON +#define DLT_I4 110 // Regulator Turn-ON time + + +// - tdt & rdt --- +// MAX GSM (not GPRS) rdt and tdt values are... +//#define rdt 380 // MAX GSM rx delta timing +//#define tdt 400 // MAX GSM tx delta timing +// but current rdt and tdt values are... +#define rdt 0 // rx delta timing +#define tdt 0 // tx delta timing + +// - RX timings --- +// - RX down: +// Flexible TPU Timings .... + +/************************************/ +/* Timing for TPU prog */ +/************************************/ +#if ( L1_TPU_DEV == 0) + #define APC_RAMP_UP_TIME 20 // maximum time for ramp up + #define APC_RAMP_DELAY 6 // minimum ramp up delay APCDEL + #define APC_RAMP_DOWN_TIME 20 // maximum ramp down time +#endif + + +#if ( L1_TPU_DEV == 1) + extern WORD16 rf_tx_tpu_timings[]; + extern WORD16 rf_rx_tpu_timings[]; + + //define for TPU Dev Mode via the arrays so that they can be tweaked later for Rx & Tx + + + + #define TRF_T1 rf_tx_tpu_timings[0] + #define TRF_T2 rf_tx_tpu_timings[1] + #define TRF_T3 rf_tx_tpu_timings[2] + #define TRF_T4 rf_tx_tpu_timings[3] + #define TRF_T5 rf_tx_tpu_timings[4] + #define TRF_T6 rf_tx_tpu_timings[5] + #define TRF_T7 rf_tx_tpu_timings[6] + #define TRF_T8 rf_tx_tpu_timings[7] + #define TRF_T9 rf_tx_tpu_timings[8] + #define TRF_T10 rf_tx_tpu_timings[9] + #define TRF_T11 rf_tx_tpu_timings[10] + #define TRF_T12 rf_tx_tpu_timings[11] + #define TRF_T13 rf_tx_tpu_timings[12] + #define TRF_T14 rf_tx_tpu_timings[13] + #define TRF_T15 rf_tx_tpu_timings[14] + #define TRF_T16 rf_tx_tpu_timings[15] + #define TRF_T17 rf_tx_tpu_timings[16] + #define TRF_T18 rf_tx_tpu_timings[17] + #define TRF_T19 rf_tx_tpu_timings[18] + #define TRF_T20 rf_tx_tpu_timings[19] + #define TRF_T21 rf_tx_tpu_timings[20] + #define TRF_T22 rf_tx_tpu_timings[21] + #define TRF_T23 rf_tx_tpu_timings[22] + #define TRF_T24 rf_tx_tpu_timings[23] + #define TRF_T25 rf_tx_tpu_timings[24] + #define TRF_T26 rf_tx_tpu_timings[25] + #define TRF_T27 rf_tx_tpu_timings[26] + #define TRF_T28 rf_tx_tpu_timings[27] + #define TRF_T29 rf_tx_tpu_timings[28] + #define TRF_T30 rf_tx_tpu_timings[29] + #define TRF_T31 rf_tx_tpu_timings[30] + #define TRF_T32 rf_tx_tpu_timings[31] + + + #define TRF_R1 rf_rx_tpu_timings[0] + #define TRF_R2 rf_rx_tpu_timings[1] + #define TRF_R3 rf_rx_tpu_timings[2] + #define TRF_R4 rf_rx_tpu_timings[3] + #define TRF_R5 rf_rx_tpu_timings[4] + #define TRF_R6 rf_rx_tpu_timings[5] + #define TRF_R7 rf_rx_tpu_timings[6] + #define TRF_R8 rf_rx_tpu_timings[7] + #define TRF_R9 rf_rx_tpu_timings[8] + #define TRF_R10 rf_rx_tpu_timings[9] + #define TRF_R11 rf_rx_tpu_timings[10] + #define TRF_R12 rf_rx_tpu_timings[11] + #define TRF_R13 rf_rx_tpu_timings[12] + #define TRF_R14 rf_rx_tpu_timings[13] + #define TRF_R15 rf_rx_tpu_timings[14] + #define TRF_R16 rf_rx_tpu_timings[15] + #define TRF_R17 rf_rx_tpu_timings[16] + #define TRF_R18 rf_rx_tpu_timings[17] + #define TRF_R19 rf_rx_tpu_timings[18] + #define TRF_R20 rf_rx_tpu_timings[19] + #define TRF_R21 rf_rx_tpu_timings[20] + #define TRF_R22 rf_rx_tpu_timings[21] + #define TRF_R23 rf_rx_tpu_timings[22] + #define TRF_R24 rf_rx_tpu_timings[23] + #define TRF_R25 rf_rx_tpu_timings[24] + #define TRF_R26 rf_rx_tpu_timings[25] + #define TRF_R27 rf_rx_tpu_timings[26] + #define TRF_R28 rf_rx_tpu_timings[27] + #define TRF_R29 rf_rx_tpu_timings[28] + #define TRF_R30 rf_rx_tpu_timings[29] + #define TRF_R31 rf_rx_tpu_timings[30] + #define TRF_R32 rf_rx_tpu_timings[31] + + //Flexi ABB Delays + // The existing #defines in the code would have to be removed and the definitions done here. + + extern WORD16 rf_flexi_abb_delays[]; + + + + #ifdef APC_RAMP_UP_TIME + #undef APC_RAMP_UP_TIME + #endif + #define APC_RAMP_UP_TIME rf_flexi_abb_delays[1] //default 32 + + + #ifdef DL_ABB_DELAY + #undef DL_ABB_DELAY + #endif + #define DL_ABB_DELAY (rf_flexi_abb_delays[2]) // ( 32L + 4L) + + + #ifdef UL_ABB_DELAY + #undef UL_ABB_DELAY + #endif + #define UL_ABB_DELAY rf_flexi_abb_delays[3] //12 + + #ifdef UL_DELAY_1RF + #undef UL_DELAY_1RF + #endif + #define UL_DELAY_1RF rf_flexi_abb_delays[4] //0 + + #ifdef UL_DELAY_2RF + #undef UL_DELAY_2RF + #endif + #define UL_DELAY_2RF rf_flexi_abb_delays[5] //0 + + #ifdef APCDEL_DOWN + #undef APCDEL_DOWN + #endif + #define APCDEL_DOWN rf_flexi_abb_delays[6] //3//3 + + #ifdef APCDEL_UP + #undef APCDEL_UP + #endif + #define APCDEL_UP rf_flexi_abb_delays[7] //24 + + #ifdef GUARD_BITS + #undef GUARD_BITS + #endif + #define GUARD_BITS rf_flexi_abb_delays[8] //7 + + #ifdef SETUP_AFC_AND_RF + #undef SETUP_AFC_AND_RF + #endif + #define SETUP_AFC_AND_RF rf_flexi_abb_delays[9] //6 + + #ifdef SERV_OFFS_REST_LOAD + #undef SERV_OFFS_REST_LOAD + #endif + #define SERV_OFFS_REST_LOAD rf_flexi_abb_delays[10] // 1L + + #ifdef TA_MAX + #undef TA_MAX + #endif + #define TA_MAX rf_flexi_abb_delays[11] // ( 63L * 4L ) + + #ifdef PRG_TX + #undef PRG_TX + #endif + #define PRG_TX rf_flexi_abb_delays[12] // (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) + + #ifdef EPSILON_OFFS + #undef EPSILON_OFFS + #endif + #define EPSILON_OFFS rf_flexi_abb_delays[14] // 2L + + #ifdef EPSILON_MEAS + #undef EPSILON_MEAS + #endif + #define EPSILON_MEAS rf_flexi_abb_delays[15]//20L + + #ifdef EPSILON_SYNC + #undef EPSILON_SYNC + #endif + #define EPSILON_SYNC rf_flexi_abb_delays[16] //10L + + #ifdef APC_RAMP_DOWN_TIME + #undef APC_RAMP_DOWN_TIME + #endif + #define APC_RAMP_DOWN_TIME rf_flexi_abb_delays[17] //32 + + #ifdef APC_RAMP_DELAY + #undef APC_RAMP_DELAY + #endif + #define APC_RAMP_DELAY rf_flexi_abb_delays[18] //6 +#endif //L1_TPU_DEV +// End Flexible TPU Timings, ABB DElays + +#if ( L1_TPU_DEV == 0) +// - RX timings --- +// - RX down: +#if (L1_MADC_ON == 1) +#define TRF_R8 (PROVISION_TIME - 170 - DLT_4B - rdt ) // for doing MADC +#endif +// The times below are offsets to when BDLENA goes down +#define TRF_R7 ( 2 - DLT_4B ) // Power down RF (idle script) +// TRF_R6 not use, warning timing TRF_R6 > TRF_R7 +#define TRF_R6 ( -20 - DLT_4B) // Disable RX Start and RF switch + +// - RX up: +// The times below are offsets to when BDLENA goes high +// Burst data comes here +#define TRF_R5 (PROVISION_TIME - 19 - DLT_1 ) // Enable RX_START +#define TRF_R4 (PROVISION_TIME - 39 - DLT_1 - rdt ) // Set RF switch for RX in selected band +#if(L1_RF_KBD_FIX == 1) +#define TRF_R3_1 (PROVISION_TIME - 89 - DLT_1 - rdt ) // Disable keyboard +#endif +#define TRF_R3 (PROVISION_TIME - 190 - DLT_4B - rdt ) // RX_ON +#define TRF_R2 (PROVISION_TIME - 197 - DLT_4B - rdt ) // Select the AGC & LNA gains +#define TRF_R1 (PROVISION_TIME - 203 - DLT_4B - rdt ) // Set RX Synth channel + + + +// - TX timings --- +// - TX down: +// The times below are offsets to when TXSTART goes down +#define TRF_T13 ( 25 - DLT_1 ) // +#define TRF_T12 ( 23 - DLT_4B ) // +#define TRF_T11 ( 16 - DLT_1 ) // +#define TRF_T10 ( 0 - DLT_1 ) // +#ifdef VARIABLE_ADC_ON_TX +#define TRF_T9 (TRF_T11-VARIABLE_ADC_ON_TX*4) +#else +#define TRF_T9 ( - 40 - DLT_1 ) // +#endif + +// - TX up: +// The times below are offsets to when TXSTART goes high +//burst data comes here +#define TRF_T8 ( 18 - DLT_1 ) // +#define TRF_T7 ( 12 - DLT_1 ) // +#define TRF_T6 ( 6 - DLT_1 ) // +#define TRF_T5 ( 0 - DLT_1 ) // +#define TRF_T4 ( - 100 - DLT_1 ) // +#if(L1_RF_KBD_FIX == 1) +#define TRF_T3_1 (-215 -DLT_1 ) // Disable keyboard +#endif +#define TRF_T3 ( - 225 - DLT_1 ) // Set APC_LDO enabled +#define TRF_T2 ( - 235 - DLT_4B - tdt ) // Power ON TX +#define TRF_T1 ( - 255 - DLT_4B - tdt ) // Set TX synth + +#endif // Non TPU DEV + + +