FreeCalypso > hg > freecalypso-schem2

changeset 46:c247abb89302

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MAX1916.v and lcd_module.v from lunalcd2
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 27 Nov 2021 01:43:32 +0000
parents 4c4eeacce681
children 9f5a3567d699
files venus/src/Makefile venus/src/periph/MAX1916.v venus/src/periph/lcd_module.v
diffstat 3 files changed, 71 insertions(+), 4 deletions(-) [+]
line wrap: on
line diff
--- a/venus/src/Makefile	Sat Nov 27 01:34:05 2021 +0000
+++ b/venus/src/Makefile	Sat Nov 27 01:43:32 2021 +0000
@@ -8,10 +8,11 @@
 	core/rfmatch_rita2pa_hb.v core/rfmatch_rita2pa_lb.v \
 	core/rita_rf_chip.v core/rita_vcxo_int.v core/rita_wrap.v \
 	core/xtal_32khz_wrap.v \
-	periph/Si9407AEY.v periph/battery.v periph/calypso_uart_in.v \
-	periph/charging_circuit.v periph/charging_led.v \
-	periph/inv_buffer_74LVC1G04.v periph/jtag_if.v \
-	periph/sim_socket_block.v periph/sim_socket_wrap.v periph/sma_wrap.v \
+	periph/MAX1916.v periph/Si9407AEY.v periph/battery.v \
+	periph/calypso_uart_in.v periph/charging_circuit.v \
+	periph/charging_led.v periph/inv_buffer_74LVC1G04.v periph/jtag_if.v \
+	periph/lcd_module.v periph/sim_socket_block.v periph/sim_socket_wrap.v \
+	periph/sma_wrap.v \
 	top/board.v top/mobile.v \
 	usb/FT2232D_block.v usb/FT2232D_chip.v usb/eeprom_93Cx6_16bit.v \
 	usb/regulator_ic.v usb/regulator_with_caps.v usb/usb_conn.v \
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/MAX1916.v	Sat Nov 27 01:43:32 2021 +0000
@@ -0,0 +1,16 @@
+module MAX1916 (GND, EN, SET, LEDK);
+
+input GND, EN, SET;
+output [1:3] LEDK;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_SOT23_6 pkg (.pin_1(EN),
+		 .pin_2(GND),
+		 .pin_3(SET),
+		 .pin_4(LEDK[3]),
+		 .pin_5(LEDK[2]),
+		 .pin_6(LEDK[1])
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/lcd_module.v	Sat Nov 27 01:43:32 2021 +0000
@@ -0,0 +1,50 @@
+module lcd_module (GND, VCI, IOVCC, DB, RD, WR, RS, CS, RESET, IM0, LEDA, LEDK);
+
+input GND, VCI, IOVCC;
+inout [15:0] DB;
+input RD, WR, RS, CS, RESET, IM0;
+input LEDA;
+input [1:3] LEDK;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+lcd_module_fp pkg (.pin_1(DB[15]),
+		   .pin_2(DB[14]),
+		   .pin_3(DB[13]),
+		   .pin_4(DB[12]),
+		   .pin_5(DB[11]),
+		   .pin_6(DB[10]),
+		   .pin_7(DB[9]),
+		   .pin_8(DB[8]),
+		   .pin_9(GND),
+		   .pin_10(DB[7]),
+		   .pin_11(DB[6]),
+		   .pin_12(DB[5]),
+		   .pin_13(DB[4]),
+		   .pin_14(DB[3]),
+		   .pin_15(DB[2]),
+		   .pin_16(DB[1]),
+		   .pin_17(DB[0]),
+		   .pin_18(IOVCC),
+		   .pin_19(VCI),
+		   .pin_20(RD),
+		   .pin_21(WR),
+		   .pin_22(RS),
+		   .pin_23(CS),
+		   .pin_24(RESET),
+		   .pin_25(IM0),
+		   .pin_26(GND),
+		   .pin_27(LEDA),
+		   .pin_28(LEDK[1]),
+		   .pin_29(LEDK[2]),
+		   .pin_30(LEDK[3]),
+		   /* the remaining pins are NC */
+		   .pin_31(),
+		   .pin_32(),
+		   .pin_33(),
+		   .pin_34(),
+		   .pin_35(),
+		   .pin_36()
+	);
+
+endmodule