--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/usb/regulator_with_caps.v	Sat Nov 20 19:44:59 2021 +0000
@@ -0,0 +1,15 @@
+module regulator_with_caps (GND, IN, OUT);
+
+input GND, IN;
+output OUT;
+
+regulator_ic reg (.IN(IN),
+		  .OUT(OUT),
+		  .GND(GND),
+		  .EN(IN)
+	);
+
+capacitor input_cap (IN, GND);
+capacitor output_cap (OUT, GND);
+
+endmodule

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/usb/usb_core.v	Sat Nov 20 19:44:59 2021 +0000
@@ -0,0 +1,66 @@
+/*
+ * This module encapsulates the USB connector, the FT2232D block and
+ * the glue components between them.
+ */
+
+module usb_core (GND, VBUS, P_5V, VCCIOA, VCCIOB,
+		 ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB, PWREN);
+
+input GND;
+output VBUS, P_5V;
+
+input VCCIOA, VCCIOB;
+inout [7:0] ADBUS, BDBUS;
+inout [3:0] ACBUS, BCBUS;
+input SI_WUA, SI_WUB;
+output PWREN;
+
+/* interconnecting wires */
+
+wire DM_connector_side, DM_chip_side;
+wire DP_connector_side, DP_chip_side;
+wire RSTOUT;
+
+usb_conn conn  (.GND(GND),
+		.VBUS(VBUS),
+		.Dminus(DM_connector_side),
+		.Dplus(DP_connector_side),
+		.ID()	/* no connect */
+	);
+
+/* ferrite bead on the power supply */
+
+inductor VBUS_ferrite (VBUS, P_5V);
+
+/* series resistors on USB data lines */
+
+resistor DM_series_R (DM_connector_side, DM_chip_side);
+resistor DP_series_R (DP_connector_side, DP_chip_side);
+
+/* we can now bring in the FT2232D block */
+
+FT2232D_block FT2232D  (.GND(GND),
+			.VCC(P_5V),
+			.VCCIOA(VCCIOA),
+			.VCCIOB(VCCIOB),
+			.USBDP(DP_chip_side),
+			.USBDM(DM_chip_side),
+			.RESET(P_5V),
+			.RSTOUT(RSTOUT),
+			.PWREN(PWREN),
+			.ADBUS(ADBUS),
+			.ACBUS(ACBUS),
+			.SI_WUA(SI_WUA),
+			.BDBUS(BDBUS),
+			.BCBUS(BCBUS),
+			.SI_WUB(SI_WUB)
+	);
+
+resistor DP_pullup_R (DP_chip_side, RSTOUT);
+
+/* power bypass caps */
+
+capacitor P_5V_cap (P_5V, GND);
+capacitor P_5V_cap2 (P_5V, GND);
+
+endmodule

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/usb/usb_domain.v	Sat Nov 20 19:44:59 2021 +0000
@@ -0,0 +1,69 @@
+/*
+ * This module encapsulates the USB domain of FC Venus.
+ */
+
+module usb_domain (GND, VBUS, Host_TxD, Host_RxD, Host_RTS, Host_CTS,
+		   Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2,
+		   RPWON, nTESTRESET);
+
+input GND;
+output VBUS;
+
+output Host_TxD, Host_RTS, Host_DTR, Host_TxD2;
+input Host_RxD, Host_CTS, Host_DCD, Host_RI, Host_RxD2;
+output RPWON, nTESTRESET;
+
+/* USB domain wires */
+
+wire P_5V, P_3V3;
+
+wire [7:0] ADBUS, BDBUS;
+wire [3:0] ACBUS, BCBUS;
+
+usb_core usb (  .GND(GND),
+		.VBUS(VBUS),
+		.P_5V(P_5V),
+		.VCCIOA(P_3V3),
+		.VCCIOB(P_3V3),
+		.ADBUS(ADBUS),
+		.ACBUS(ACBUS),
+		.SI_WUA(P_3V3),
+		.BDBUS(BDBUS),
+		.BCBUS(BCBUS),
+		.SI_WUB(P_3V3),
+		.PWREN()	/* no connect */
+	);
+
+regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3));
+
+usb_domain_buf buf (.GND(GND),
+		    .P_3V3(P_3V3),
+		    .Int_TxD(ADBUS[0]),
+		    .Int_RxD(ADBUS[1]),
+		    .Int_RTS(ADBUS[2]),
+		    .Int_CTS(ADBUS[3]),
+		    .Int_DTR(ADBUS[4]),
+		    .Int_DCD(ADBUS[6]),
+		    .Int_RI(ADBUS[7]),
+		    .Int_TxD2(BDBUS[0]),
+		    .Int_RxD2(BDBUS[1]),
+		    .Host_TxD(Host_TxD),
+		    .Host_RxD(Host_RxD),
+		    .Host_RTS(Host_RTS),
+		    .Host_CTS(Host_CTS),
+		    .Host_DTR(Host_DTR),
+		    .Host_DCD(Host_DCD),
+		    .Host_RI(Host_RI),
+		    .Host_TxD2(Host_TxD2),
+		    .Host_RxD2(Host_RxD2)
+	);
+
+usb_domain_bctl bctl (  .GND(GND),
+			.P_3V3(P_3V3),
+			.ChanB_RTS(BDBUS[2]),
+			.ChanB_DTR(BDBUS[4]),
+			.CTL1_out(RPWON),
+			.CTL2_out(nTESTRESET)
+	);
+
+endmodule

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/usb/usb_domain_bctl.v	Sat Nov 20 19:44:59 2021 +0000
@@ -0,0 +1,27 @@
+/*
+ * This module encapsulates the USB domain circuit for boot control.
+ */
+
+module usb_domain_bctl (GND, P_3V3, ChanB_RTS, ChanB_DTR, CTL1_out, CTL2_out);
+
+input GND, P_3V3;
+input ChanB_RTS, ChanB_DTR;
+output CTL1_out, CTL2_out;
+
+/* pull-up resistors on FT2232D outputs */
+
+resistor ChanB_RTS_pullup (ChanB_RTS, P_3V3);
+resistor ChanB_DTR_pullup (ChanB_DTR, P_3V3);
+
+/* open drain buffers */
+
+logic_ic_common od_buf_common ( .Vcc(P_3V3),
+				.GND(GND)
+	);
+
+capacitor od_buf_bypass_cap (P_3V3, GND);
+
+buffer_slot_basic buf_CTL1 (.A(ChanB_RTS), .Y(CTL1_out));
+buffer_slot_basic buf_CTL2 (.A(ChanB_DTR), .Y(CTL2_out));
+
+endmodule

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/usb/usb_domain_buf.v	Sat Nov 20 19:44:59 2021 +0000
@@ -0,0 +1,46 @@
+/*
+ * This module encapsulates the 74LVC541A buffer in the USB domain.
+ */
+
+module usb_domain_buf  (GND, P_3V3,
+			Int_TxD, Int_RxD, Int_RTS, Int_CTS,
+			Int_DTR, Int_DCD, Int_RI, Int_TxD2, Int_RxD2,
+			Host_TxD, Host_RxD, Host_RTS, Host_CTS,
+			Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2);
+
+input GND, P_3V3;
+
+input Int_TxD, Int_RTS, Int_DTR, Int_TxD2;
+output Int_RxD, Int_CTS, Int_DCD, Int_RI, Int_RxD2;
+
+output Host_TxD, Host_RTS, Host_DTR, Host_TxD2;
+input Host_RxD, Host_CTS, Host_DCD, Host_RI, Host_RxD2;
+
+/* buffer common part */
+
+x541_common common (.Vcc(P_3V3),
+		    .GND(GND),
+		    .nOE1(GND),
+		    .nOE2(GND)
+	);
+
+capacitor bypass_cap (P_3V3, GND);
+
+/* input buffers */
+
+buffer_slot_basic buf_RxD  (.A(Host_RxD),  .Y(Int_RxD));
+buffer_slot_basic buf_CTS  (.A(Host_CTS),  .Y(Int_CTS));
+buffer_slot_basic buf_DCD  (.A(Host_DCD),  .Y(Int_DCD));
+buffer_slot_basic buf_RI   (.A(Host_RI),   .Y(Int_RI));
+buffer_slot_basic buf_RxD2 (.A(Host_RxD2), .Y(Int_RxD2));
+
+/* output buffers */
+
+buffer_slot_basic buf_TxD  (.A(Int_TxD),  .Y(Host_TxD));
+buffer_slot_basic buf_DTR  (.A(Int_DTR),  .Y(Host_DTR));
+buffer_slot_basic buf_TxD2 (.A(Int_TxD2), .Y(Host_TxD2));
+
+/* RTS direct pass-thru: use an 0402 0R jumper */
+resistor jmp_RTS (Int_RTS, Host_RTS);
+
+endmodule