--- a/venus/src/core/dbb_block.v	Fri Dec 10 05:58:58 2021 +0000
+++ b/venus/src/core/dbb_block.v	Fri Dec 10 06:20:19 2021 +0000
@@ -7,6 +7,9 @@
  * - nBSCAN and nEMU[1:0] no-connects.
  *
  * All other Calypso signals are passed through untouched.
+ *
+ * The buffer that produces a 2.8V version of the ON_nOFF signal for
+ * flash reset is also included here.
  */
 
 module dbb_block (GND, Vdbb, Vio, Vflash, Vrtc,
@@ -24,7 +27,7 @@
 		  BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
 		  VDX, VDR, VFSRX, VCLKRX,
 		  MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
-		  SIM_IO, SIM_CLK, SIM_RST, SIM_CD);
+		  SIM_IO, SIM_CLK, SIM_RST, SIM_CD, ON_nOFF_2V8);
 
 input GND, Vdbb, Vio, Vflash, Vrtc;
 
@@ -80,6 +83,8 @@
 output SIM_CLK, SIM_RST;
 input SIM_CD;
 
+output ON_nOFF_2V8;
+
 /* nets inside this module */
 wire SIM_PWCTRL;
 wire GND_32khz, OSC32K_IN, OSC32K_OUT, OSC32K_OUT_2;
@@ -209,4 +214,13 @@
 /* SIM_PWCTRL resistor like on Leonardo schematics */
 resistor R207 (SIM_PWCTRL, SIM_IO);
 
+/* ON_nOFF_2V8 buffer */
+
+buffer_74AXP1T34 ON_nOFF_2V8_buffer (.GND(GND),
+				     .Vcci(VDD_CORE),
+				     .Vcco(Vflash),
+				     .A(ON_OFF),
+				     .Y(ON_nOFF_2V8)
+	);
+
 endmodule