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comparison venus/src/core/dbb_block.v @ 86:adc84e0e98d6

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add 74AXP1T34 buffer for flash reset
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 10 Dec 2021 06:20:19 +0000
parents 971c05950675
children
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equal deleted inserted replaced
85:93b238ad7d6e 86:adc84e0e98d6
5 * - the 32 kHz xtal circuit with its special ground; 5 * - the 32 kHz xtal circuit with its special ground;
6 * - nIBOOT, IDDQ and SIM_PWCTRL tie-offs; 6 * - nIBOOT, IDDQ and SIM_PWCTRL tie-offs;
7 * - nBSCAN and nEMU[1:0] no-connects. 7 * - nBSCAN and nEMU[1:0] no-connects.
8 * 8 *
9 * All other Calypso signals are passed through untouched. 9 * All other Calypso signals are passed through untouched.
10 *
11 * The buffer that produces a 2.8V version of the ON_nOFF signal for
12 * flash reset is also included here.
10 */ 13 */
11 14
12 module dbb_block (GND, Vdbb, Vio, Vflash, Vrtc, 15 module dbb_block (GND, Vdbb, Vio, Vflash, Vrtc,
13 TSPCLKX, TSPDO, TSPDI_IO4, TSPEN, TSPACT, 16 TSPCLKX, TSPDO, TSPDI_IO4, TSPEN, TSPACT,
14 DATA, ADD, RnW, nFWE, nFOE, FDP, nBLE, nBHE, nCS, 17 DATA, ADD, RnW, nFWE, nFOE, FDP, nBLE, nBHE, nCS,
22 TCXOEN, RFEN, ON_OFF, IT_WAKEUP, 25 TCXOEN, RFEN, ON_OFF, IT_WAKEUP,
23 TDI, TDO, TCK, TMS, 26 TDI, TDO, TCK, TMS,
24 BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK, 27 BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
25 VDX, VDR, VFSRX, VCLKRX, 28 VDX, VDR, VFSRX, VCLKRX,
26 MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13, 29 MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
27 SIM_IO, SIM_CLK, SIM_RST, SIM_CD); 30 SIM_IO, SIM_CLK, SIM_RST, SIM_CD, ON_nOFF_2V8);
28 31
29 input GND, Vdbb, Vio, Vflash, Vrtc; 32 input GND, Vdbb, Vio, Vflash, Vrtc;
30 33
31 output TSPCLKX, TSPDO; 34 output TSPCLKX, TSPDO;
32 inout TSPDI_IO4; 35 inout TSPDI_IO4;
77 output MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13; 80 output MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13;
78 81
79 inout SIM_IO; 82 inout SIM_IO;
80 output SIM_CLK, SIM_RST; 83 output SIM_CLK, SIM_RST;
81 input SIM_CD; 84 input SIM_CD;
85
86 output ON_nOFF_2V8;
82 87
83 /* nets inside this module */ 88 /* nets inside this module */
84 wire SIM_PWCTRL; 89 wire SIM_PWCTRL;
85 wire GND_32khz, OSC32K_IN, OSC32K_OUT, OSC32K_OUT_2; 90 wire GND_32khz, OSC32K_IN, OSC32K_OUT, OSC32K_OUT_2;
86 wire VDD_PLL, VDD_CORE; 91 wire VDD_PLL, VDD_CORE;
207 capacitor C201 (Vrtc, GND_32khz); 212 capacitor C201 (Vrtc, GND_32khz);
208 213
209 /* SIM_PWCTRL resistor like on Leonardo schematics */ 214 /* SIM_PWCTRL resistor like on Leonardo schematics */
210 resistor R207 (SIM_PWCTRL, SIM_IO); 215 resistor R207 (SIM_PWCTRL, SIM_IO);
211 216
217 /* ON_nOFF_2V8 buffer */
218
219 buffer_74AXP1T34 ON_nOFF_2V8_buffer (.GND(GND),
220 .Vcci(VDD_CORE),
221 .Vcco(Vflash),
222 .A(ON_OFF),
223 .Y(ON_nOFF_2V8)
224 );
225
212 endmodule 226 endmodule