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R407 intnoconn: use different terminal numbering on further thought
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 05 Dec 2021 03:49:14 +0000
parents 1d2b57d4f1c9
children
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78:2dc128ba1659 79:cf39d9352394
32 32
33 More specifically, the Mother's idea is that the subcircuit representing R407 33 More specifically, the Mother's idea is that the subcircuit representing R407
34 will have 4 terminals rather than 2, with terminal numbers assigned as follows: 34 will have 4 terminals rather than 2, with terminal numbers assigned as follows:
35 35
36 Pin 1 = resistor side 1, surface layer 36 Pin 1 = resistor side 1, surface layer
37 Pin 2 = resistor side 1, inner layer 37 Pin 2 = resistor side 2, surface layer
38 Pin 3 = resistor side 2, surface layer 38 Pin 3 = resistor side 1, inner layer
39 Pin 4 = resistor side 2, inner layer 39 Pin 4 = resistor side 2, inner layer
40 40
41 The idea is to include in-pad microvias going one layer down inside the 41 The idea is to include in-pad microvias going one layer down inside the
42 subcircuit, and put terminals 2 and 4 on the inner layer. Terminals 1 & 2 will 42 subcircuit, and put terminals 3 and 4 on the inner layer. Terminals 1 & 3 will
43 form one intnoconn group, and terminals 3 & 4 will form the other intnoconn 43 form one intnoconn group, and terminals 2 & 4 will form the other intnoconn
44 group. Surface traces carrying the charging current will connect to terminals 44 group. Surface traces carrying the charging current will connect to terminals
45 1 and 3, whereas sensing nets VCCS and VBATS will connect to terminals 2 and 4 45 1 and 2, whereas sensing nets VCCS and VBATS will connect to terminals 3 and 4
46 on the inner layer. 46 on the inner layer.
47 47
48 Our current ueda source implements this idea at the netlist level; creation of 48 Our current ueda source implements this idea at the netlist level; creation of
49 the corresponding pcb-rnd subcircuit remains TBD. 49 the corresponding pcb-rnd subcircuit remains TBD.