FreeCalypso > hg > freecalypso-reveng
changeset 4:a821df9c4457
boot ROM re: got as far as UART init
| author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
|---|---|
| date | Tue, 16 Apr 2013 05:36:59 +0000 |
| parents | e3f8fe6a848e |
| children | 9db4dcf94128 |
| files | bootrom.disasm |
| diffstat | 1 files changed, 48 insertions(+), 10 deletions(-) [+] |
line wrap: on
line diff
--- a/bootrom.disasm Mon Apr 15 16:18:53 2013 +0000 +++ b/bootrom.disasm Tue Apr 16 05:36:59 2013 +0000 @@ -926,6 +926,16 @@ e24: 00800108 addeq r0, r0, r8, lsl #2 e28: 00800528 addeq r0, r0, r8, lsr #10 +; The following routine performs basic sanity initialization +; of the memory map and clocking. +; +; Arguments: +; R0: WS setting for nCS0 (external ROM/flash) +; R1: WS setting for nCS6 (internal RAM) +; R2: WS setting for nCS7 (internal ROM) +; R3: value to be written into bits <3:0> of FFFF:F900 +; stack arg: value to be written into bits <7:4> of FFFF:F900 + e2c: e92d4070 stmdb sp!, {r4, r5, r6, lr} e30: e5dd5010 ldrb r5, [sp, #16] ; mask all interrupts @@ -969,19 +979,22 @@ ea4: e20cccff and r12, r12, #65280 ; 0xff00 ea8: e184c00c orr r12, r4, r12 eac: e1c6c0b2 strh r12, [r6, #2] - +; program nCS0: WS as given by R0, 1 dummy cycle, enable writes eb0: e3a0cc02 mov r12, #512 ; 0x200 eb4: e200001f and r0, r0, #31 ; 0x1f eb8: e3800e2a orr r0, r0, #672 ; 0x2a0 ebc: e10600bc strh r0, [r6, -r12] +; program nCS6 (int RAM): WS as given by R1, common sense values for the rest ec0: e3a0cf7d mov r12, #500 ; 0x1f4 ec4: e201001f and r0, r1, #31 ; 0x1f ec8: e38000c0 orr r0, r0, #192 ; 0xc0 ecc: e10600bc strh r0, [r6, -r12] +; program nCS7 (int ROM): same as nCS6, but WS as given by R2 ed0: e3a0cf7e mov r12, #504 ; 0x1f8 ed4: e202001f and r0, r2, #31 ; 0x1f ed8: e38000c0 orr r0, r0, #192 ; 0xc0 edc: e10600bc strh r0, [r6, -r12] +; program FFFF:F900 with {FF,stack_arg,R3} ee0: e3a0cb01 mov r12, #1024 ; 0x400 ee4: e1830205 orr r0, r3, r5, lsl #4 ee8: e3800cff orr r0, r0, #65280 ; 0xff00 @@ -1180,6 +1193,8 @@ ; main() entry point 11d8: e92d4070 stmdb sp!, {r4, r5, r6, lr} 11dc: e24dd008 sub sp, sp, #8 ; 0x8 +; 0xe2c basic memmap/clock init routine called with the following +; values: WS=4 for nCS0, WS=0 for nCS6 and nCS7, FF22 into FFFF:F900 11e0: e3a0c002 mov r12, #2 ; 0x2 11e4: e5cdc000 strb r12, [sp] 11e8: e3a00004 mov r0, #4 ; 0x4 @@ -1187,7 +1202,7 @@ 11f0: e3a02000 mov r2, #0 ; 0x0 11f4: e3a03002 mov r3, #2 ; 0x2 11f8: ebffff0b bl 0xe2c - 11fc: eb00004f bl 0x1340 + 11fc: eb00004f bl 0x1340 ; init UARTs 1200: e59f00f4 ldr r0, [pc, #244] ; 0x12fc 1204: e3a0c802 mov r12, #131072 ; 0x20000 1208: e24ccdad sub r12, r12, #11072 ; 0x2b40 @@ -1272,8 +1287,13 @@ 1338: 1afffff6 bne 0x1318 133c: e12fff1e bx lr +; The following routine initializes both UARTs with a fixed set of +; parameters (the same for both UARTs). + 1340: e92d4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - 1344: e59fc144 ldr r12, [pc, #324] ; 0x1490 +; UIR fiddling: connect the MODEM UART to the MCU +; and restore normal operation (interrupts NOT masked at UIR level) + 1344: e59fc144 ldr r12, =0xFFFF6000 ; via 0x1490 1348: e5dc0000 ldrb r0, [r12] 134c: e3800002 orr r0, r0, #2 ; 0x2 1350: e5cc0000 strb r0, [r12] @@ -1283,6 +1303,7 @@ 1360: e5dc0000 ldrb r0, [r12] 1364: e20000fd and r0, r0, #253 ; 0xfd 1368: e5cc0000 strb r0, [r12] +; actual UART register diddling: prepare the values for both UARTs 136c: e3a0b003 mov r11, #3 ; 0x3 1370: e3a05000 mov r5, #0 ; 0x0 1374: e3a0a02a mov r10, #42 ; 0x2a @@ -1290,22 +1311,36 @@ 137c: e3a070bf mov r7, #191 ; 0xbf 1380: e3a04007 mov r4, #7 ; 0x7 1384: e3a02002 mov r2, #2 ; 0x2 - 1388: e59f60fc ldr r6, [pc, #252] ; 0x148c +; loop over the 2 UART base addresses + 1388: e59f60fc ldr r6, =0x1FCC ; via 0x148c 138c: e496c004 ldr r12, [r6], #4 1390: e28c3008 add r3, r12, #8 ; 0x8 +; R3 points to register 8 (MDR1) +; write 07 into it: reset mode 1394: e5c34000 strb r4, [r3] 1398: e28c0003 add r0, r12, #3 ; 0x3 +; R0 points to register 3 (LCR) +; write BF into it: map in the extended registers 139c: e5c07000 strb r7, [r0] 13a0: e28c1002 add r1, r12, #2 ; 0x2 +; R1 points to register 2: EFR under current mapping +; set bit 4: enable enhanced functions 13a4: e5d18000 ldrb r8, [r1] 13a8: e3888010 orr r8, r8, #16 ; 0x10 13ac: e5c18000 strb r8, [r1] +; write 80 into LCR: map in the baud rate divisor registers 13b0: e5c09000 strb r9, [r0] +; reg 2 (pointed to by R1) is now IIR/FCR +; write 07 into FCR: FIFOs enabled and cleared, no DMA 13b4: e5c14000 strb r4, [r1] +; write BF into LCR again 13b8: e5c07000 strb r7, [r0] +; load baud rate divisor /42 13bc: e5cca000 strb r10, [r12] 13c0: e5cc5001 strb r5, [r12, #1] +; write 03 into LCR: restore normal registers, 8N1 13c4: e5c0b000 strb r11, [r0] +; write 00 into MDR1: plain UART mode 13c8: e5c35000 strb r5, [r3] 13cc: e2522001 subs r2, r2, #1 ; 0x1 13d0: 1affffed bne 0x138c @@ -1358,9 +1393,10 @@ 1484: e3a00000 mov r0, #0 ; 0x0 1488: e12fff1e bx lr - 148c: 00001fcc andeq r1, r0, r12, asr #31 - 1490: ffff6000 swinv 0x00ff6000 - 1494: 00001fd4 ldreqd r1, [r0], -r4 +; literal pool + 148c: 00001fcc + 1490: ffff6000 + 1494: 00001fd4 ; The RESET entry point branches here ; @@ -1719,10 +1755,12 @@ 00001FE0: 24 F0 1F E5 24 F0 1F E5 24 F0 1F E5 24 F0 1F E5 $...$...$...$... 00001FF0: 24 F0 1F E5 24 F0 1F E5 24 F0 1F E5 00 00 00 03 $...$...$....... -; The filler appears to end at 0x1FCC. Then we've got some data words: +; The filler ends at 0x1FCC. Then we've got some data words: - 1fcc: ffff5800 swinv 0x00ff5800 - 1fd0: ffff5000 swinv 0x00ff5000 +; base addresses of the two UARTs + 1fcc: ffff5800 + 1fd0: ffff5000 +; ??? 1fd4: 0e000700 cdpeq 7, 0, cr0, cr0, cr0, {0} 1fd8: 1c001500 cfstr32ne mvfx1, [r0] 1fdc: 00002a00 andeq r2, r0, r0, lsl #20