FreeCalypso > hg > freecalypso-reveng

changeset 251:6d9a6627b085

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pirelli/fw-disasm: continuing Switch_ON() analysis
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 24 Dec 2017 18:03:25 +0000
parents 431efc676a9c
children 2eae53bb4a4e
files pirelli/fw-disasm
diffstat 1 files changed, 285 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/pirelli/fw-disasm	Sun Dec 24 17:18:06 2017 +0000
+++ b/pirelli/fw-disasm	Sun Dec 24 18:03:25 2017 +0000
@@ -638,6 +638,285 @@
   31c752:	f0dc fccb	bl	0x3f90ec	; $initialize_l1pvar
   31c756:	bd30		pop	{r4, r5, pc}
 
+; The following function takes a raw ADC VBAT measurement
+; as input (R0) and returns the mV value per the calibration.
+  32dae8:	498b		ldr	r1, =0x801734	; via 0x32dd18
+  32daea:	880a		ldrh	r2, [r1, #0]
+  32daec:	4342		mul	r2, r0
+  32daee:	0a90		lsr	r0, r2, #10
+  32daf0:	8a49		ldrh	r1, [r1, #18]	; 0x12
+  32daf2:	1808		add	r0, r1, r0
+  32daf4:	0400		lsl	r0, r0, #16
+  32daf6:	0c00		lsr	r0, r0, #16
+  32daf8:	4770		bx	lr
+
+  32dafa:	b500		push	{lr}
+  32dafc:	49c2		ldr	r1, =0x1774e70	; via 0x32de08
+  32dafe:	6809		ldr	r1, [r1, #0]
+  32db00:	8909		ldrh	r1, [r1, #8]
+  32db02:	4288		cmp	r0, r1
+  32db04:	dc01		bgt	0x32db0a
+  32db06:	2000		mov	r0, #0
+  32db08:	bd00		pop	{pc}
+  32db0a:	1a40		sub	r0, r0, r1
+  32db0c:	4983		ldr	r1, =0x357	; via 0x32dd1c
+  32db0e:	4348		mul	r0, r1
+  32db10:	217d		mov	r1, #125	; 0x7d
+  32db12:	00c9		lsl	r1, r1, #3
+  32db14:	f0c9 fb8a	bl	0x3f722c
+  32db18:	0408		lsl	r0, r1, #16
+  32db1a:	0c00		lsr	r0, r0, #16
+  32db1c:	bd00		pop	{pc}
+
+  32db1e:	b510		push	{r4, lr}
+  32db20:	b082		sub	sp, #8
+  32db22:	1c04		add	r4, r0, #0
+  32db24:	48b9		ldr	r0, =0xa0020	; via 0x32de0c
+  32db26:	9000		str	r0, [sp, #0]
+  32db28:	a0c8		add	r0, pc, #800	; 0x320
+  32db2a:	2126		mov	r1, #38	; 0x26
+  32db2c:	1c22		add	r2, r4, #0
+  32db2e:	2305		mov	r3, #5
+  32db30:	f0ad f880	bl	0x3dac34
+  32db34:	2c32		cmp	r4, #50	; 0x32
+  32db36:	da0c		bge	0x32db52
+  32db38:	2c00		cmp	r4, #0
+  32db3a:	dd0a		ble	0x32db52
+  32db3c:	48b3		ldr	r0, =0xa0020	; via 0x32de0c
+  32db3e:	9000		str	r0, [sp, #0]
+  32db40:	a0cc		add	r0, pc, #816	; 0x330
+  32db42:	2121		mov	r1, #33	; 0x21
+  32db44:	2200		mov	r2, #0
+  32db46:	43d2		mvn	r2, r2
+  32db48:	2305		mov	r3, #5
+  32db4a:	f0ad f873	bl	0x3dac34
+  32db4e:	2001		mov	r0, #1
+  32db50:	e01c		b	0x32db8c
+  32db52:	2148		mov	r1, #72	; 0x48
+  32db54:	48ac		ldr	r0, =0x1774e70	; via 0x32de08
+  32db56:	6800		ldr	r0, [r0, #0]
+  32db58:	5c08		ldrb	r0, [r1, r0]
+  32db5a:	2801		cmp	r0, #1
+  32db5c:	d104		bne	0x32db68
+  32db5e:	48ab		ldr	r0, =0xa0020	; via 0x32de0c
+  32db60:	9000		str	r0, [sp, #0]
+  32db62:	a0cd		add	r0, pc, #820	; 0x334
+  32db64:	2117		mov	r1, #23	; 0x17
+  32db66:	e7ed		b	0x32db44
+  32db68:	2c32		cmp	r4, #50	; 0x32
+  32db6a:	db01		blt	0x32db70
+  32db6c:	2003		mov	r0, #3
+  32db6e:	e000		b	0x32db72
+  32db70:	2004		mov	r0, #4
+  32db72:	43c0		mvn	r0, r0
+  32db74:	49b4		ldr	r1, =0x1774b78	; via 0x32de48
+  32db76:	8008		strh	r0, [r1, #0]
+  32db78:	48a4		ldr	r0, =0xa0020	; via 0x32de0c
+  32db7a:	9000		str	r0, [sp, #0]
+  32db7c:	a0cc		add	r0, pc, #816	; 0x330
+  32db7e:	2122		mov	r1, #34	; 0x22
+  32db80:	2200		mov	r2, #0
+  32db82:	43d2		mvn	r2, r2
+  32db84:	2304		mov	r3, #4
+  32db86:	f0ad f855	bl	0x3dac34
+  32db8a:	2000		mov	r0, #0
+  32db8c:	b002		add	sp, #8
+  32db8e:	bd10		pop	{r4, pc}
+
+  32dfee:	b510		push	{r4, lr}
+  32dff0:	b082		sub	sp, #8
+  32dff2:	1c04		add	r4, r0, #0
+  32dff4:	f000 f9a4	bl	0x32e340
+  32dff8:	4669		mov	r1, sp
+  32dffa:	8048		strh	r0, [r1, #2]
+  32dffc:	48ce		ldr	r0, =0x17729d0	; via 0x32e338
+  32dffe:	884a		ldrh	r2, [r1, #2]
+  32e000:	8801		ldrh	r1, [r0, #0]
+  32e002:	428a		cmp	r2, r1
+  32e004:	db1b		blt	0x32e03e
+  32e006:	2101		mov	r1, #1
+  32e008:	e002		b	0x32e010
+  32e00a:	4669		mov	r1, sp
+  32e00c:	8809		ldrh	r1, [r1, #0]
+  32e00e:	3101		add	r1, #1
+  32e010:	466a		mov	r2, sp
+  32e012:	8011		strh	r1, [r2, #0]
+  32e014:	4669		mov	r1, sp
+  32e016:	8809		ldrh	r1, [r1, #0]
+  32e018:	2903		cmp	r1, #3
+  32e01a:	da07		bge	0x32e02c
+  32e01c:	4669		mov	r1, sp
+  32e01e:	8809		ldrh	r1, [r1, #0]
+  32e020:	0089		lsl	r1, r1, #2
+  32e022:	5a41		ldrh	r1, [r0, r1]
+  32e024:	466a		mov	r2, sp
+  32e026:	8852		ldrh	r2, [r2, #2]
+  32e028:	428a		cmp	r2, r1
+  32e02a:	daee		bge	0x32e00a
+  32e02c:	4669		mov	r1, sp
+  32e02e:	8809		ldrh	r1, [r1, #0]
+  32e030:	0089		lsl	r1, r1, #2
+  32e032:	1840		add	r0, r0, r1
+  32e034:	3802		sub	r0, #2
+  32e036:	8801		ldrh	r1, [r0, #0]
+  32e038:	4668		mov	r0, sp
+  32e03a:	8081		strh	r1, [r0, #4]
+  32e03c:	e002		b	0x32e044
+  32e03e:	4669		mov	r1, sp
+  32e040:	2000		mov	r0, #0
+  32e042:	8088		strh	r0, [r1, #4]
+  32e044:	4668		mov	r0, sp
+  32e046:	8880		ldrh	r0, [r0, #4]
+  32e048:	1900		add	r0, r0, r4
+  32e04a:	0400		lsl	r0, r0, #16
+  32e04c:	0c04		lsr	r4, r0, #16
+  32e04e:	4abb		ldr	r2, =0x177297c	; via 0x32e33c
+  32e050:	8810		ldrh	r0, [r2, #0]
+  32e052:	4284		cmp	r4, r0
+  32e054:	db01		blt	0x32e05a
+  32e056:	7890		ldrb	r0, [r2, #2]
+  32e058:	e022		b	0x32e0a0
+  32e05a:	2001		mov	r0, #1
+  32e05c:	e002		b	0x32e064
+  32e05e:	4668		mov	r0, sp
+  32e060:	8800		ldrh	r0, [r0, #0]
+  32e062:	3001		add	r0, #1
+  32e064:	4669		mov	r1, sp
+  32e066:	8008		strh	r0, [r1, #0]
+  32e068:	4668		mov	r0, sp
+  32e06a:	8800		ldrh	r0, [r0, #0]
+  32e06c:	2815		cmp	r0, #21	; 0x15
+  32e06e:	db0c		blt	0x32e08a
+  32e070:	4668		mov	r0, sp
+  32e072:	8800		ldrh	r0, [r0, #0]
+  32e074:	2815		cmp	r0, #21	; 0x15
+  32e076:	d106		bne	0x32e086
+  32e078:	4668		mov	r0, sp
+  32e07a:	8800		ldrh	r0, [r0, #0]
+  32e07c:	0080		lsl	r0, r0, #2
+  32e07e:	1810		add	r0, r2, r0
+  32e080:	3802		sub	r0, #2
+  32e082:	7800		ldrb	r0, [r0, #0]
+  32e084:	e00c		b	0x32e0a0
+  32e086:	2000		mov	r0, #0
+  32e088:	e00a		b	0x32e0a0
+  32e08a:	4668		mov	r0, sp
+  32e08c:	8800		ldrh	r0, [r0, #0]
+  32e08e:	0080		lsl	r0, r0, #2
+  32e090:	5a10		ldrh	r0, [r2, r0]
+  32e092:	4284		cmp	r4, r0
+  32e094:	dde3		ble	0x32e05e
+  32e096:	4668		mov	r0, sp
+  32e098:	8800		ldrh	r0, [r0, #0]
+  32e09a:	0080		lsl	r0, r0, #2
+  32e09c:	1810		add	r0, r2, r0
+  32e09e:	7880		ldrb	r0, [r0, #2]
+  32e0a0:	b002		add	sp, #8
+  32e0a2:	bd10		pop	{r4, pc}
+
+  32e340:	b510		push	{r4, lr}
+  32e342:	b08c		sub	sp, #48	; 0x30
+  32e344:	f0b0 ffbd	bl	0x3df2c2
+  32e348:	1c04		add	r4, r0, #0
+  32e34a:	484a		ldr	r0, =0x357	; via 0x32e474
+  32e34c:	4360		mul	r0, r4
+  32e34e:	217d		mov	r1, #125	; 0x7d
+  32e350:	00c9		lsl	r1, r1, #3
+  32e352:	f0c8 ff6b	bl	0x3f722c
+  32e356:	0408		lsl	r0, r1, #16
+  32e358:	1404		asr	r4, r0, #16
+  32e35a:	f085 fea4	bl	0x3b40a6
+  32e35e:	2800		cmp	r0, #0
+  32e360:	d002		beq	0x32e368
+  32e362:	34e6		add	r4, #230	; 0xe6
+  32e364:	0420		lsl	r0, r4, #16
+  32e366:	1404		asr	r4, r0, #16
+  32e368:	483f		ldr	r0, =0x8036a8	; via 0x32e468
+  32e36a:	6800		ldr	r0, [r0, #0]
+  32e36c:	2802		cmp	r0, #2
+  32e36e:	d805		bhi	0x32e37c
+  32e370:	f085 fe99	bl	0x3b40a6
+  32e374:	2800		cmp	r0, #0
+  32e376:	d14a		bne	0x32e40e
+  32e378:	3432		add	r4, #50	; 0x32
+  32e37a:	e046		b	0x32e40a
+  32e37c:	4668		mov	r0, sp
+  32e37e:	f0c9 fe35	bl	0x3f7fec
+  32e382:	4668		mov	r0, sp
+  32e384:	7800		ldrb	r0, [r0, #0]
+  32e386:	2800		cmp	r0, #0
+  32e388:	d137		bne	0x32e3fa
+  32e38a:	4668		mov	r0, sp
+  32e38c:	7880		ldrb	r0, [r0, #2]
+  32e38e:	1ec0		sub	r0, r0, #3
+  32e390:	2800		cmp	r0, #0
+  32e392:	d00b		beq	0x32e3ac
+  32e394:	3801		sub	r0, #1
+  32e396:	2800		cmp	r0, #0
+  32e398:	d015		beq	0x32e3c6
+  32e39a:	3801		sub	r0, #1
+  32e39c:	2800		cmp	r0, #0
+  32e39e:	d00c		beq	0x32e3ba
+  32e3a0:	3801		sub	r0, #1
+  32e3a2:	2800		cmp	r0, #0
+  32e3a4:	d004		beq	0x32e3b0
+  32e3a6:	3802		sub	r0, #2
+  32e3a8:	2800		cmp	r0, #0
+  32e3aa:	d10a		bne	0x32e3c2
+  32e3ac:	2202		mov	r2, #2
+  32e3ae:	e00b		b	0x32e3c8
+  32e3b0:	4668		mov	r0, sp
+  32e3b2:	8980		ldrh	r0, [r0, #12]	; 0xc
+  32e3b4:	28af		cmp	r0, #175	; 0xaf
+  32e3b6:	db04		blt	0x32e3c2
+  32e3b8:	e005		b	0x32e3c6
+  32e3ba:	4668		mov	r0, sp
+  32e3bc:	8980		ldrh	r0, [r0, #12]	; 0xc
+  32e3be:	287d		cmp	r0, #125	; 0x7d
+  32e3c0:	da01		bge	0x32e3c6
+  32e3c2:	2200		mov	r2, #0
+  32e3c4:	e000		b	0x32e3c8
+  32e3c6:	2201		mov	r2, #1
+  32e3c8:	4668		mov	r0, sp
+  32e3ca:	7d00		ldrb	r0, [r0, #20]	; 0x14
+  32e3cc:	2814		cmp	r0, #20	; 0x14
+  32e3ce:	db02		blt	0x32e3d6
+  32e3d0:	2013		mov	r0, #19	; 0x13
+  32e3d2:	4669		mov	r1, sp
+  32e3d4:	7508		strb	r0, [r1, #20]	; 0x14
+  32e3d6:	4669		mov	r1, sp
+  32e3d8:	7c89		ldrb	r1, [r1, #18]	; 0x12
+  32e3da:	2900		cmp	r1, #0
+  32e3dc:	d004		beq	0x32e3e8
+  32e3de:	2114		mov	r1, #20	; 0x14
+  32e3e0:	4351		mul	r1, r2
+  32e3e2:	1840		add	r0, r0, r1
+  32e3e4:	4921		ldr	r1, =0x52e31c	; via 0x32e46c
+  32e3e6:	e003		b	0x32e3f0
+  32e3e8:	2114		mov	r1, #20	; 0x14
+  32e3ea:	4351		mul	r1, r2
+  32e3ec:	1840		add	r0, r0, r1
+  32e3ee:	4920		ldr	r1, =0x52e394	; via 0x32e470
+  32e3f0:	0040		lsl	r0, r0, #1
+  32e3f2:	5a08		ldrh	r0, [r1, r0]
+  32e3f4:	1900		add	r0, r0, r4
+  32e3f6:	0400		lsl	r0, r0, #16
+  32e3f8:	e001		b	0x32e3fe
+  32e3fa:	3496		add	r4, #150	; 0x96
+  32e3fc:	0420		lsl	r0, r4, #16
+  32e3fe:	1404		asr	r4, r0, #16
+  32e400:	f085 fe51	bl	0x3b40a6
+  32e404:	2800		cmp	r0, #0
+  32e406:	d002		beq	0x32e40e
+  32e408:	3c32		sub	r4, #50	; 0x32
+  32e40a:	0420		lsl	r0, r4, #16
+  32e40c:	1404		asr	r4, r0, #16
+  32e40e:	0420		lsl	r0, r4, #16
+  32e410:	0c00		lsr	r0, r0, #16
+  32e412:	b00c		add	sp, #48	; 0x30
+  32e414:	bd10		pop	{r4, pc}
+  32e416:	46c0		nop			(mov r8, r8)
+
 $ABB_Sem_Create:
   3491ee:	b500		push	{lr}
   3491f0:	48f2		ldr	r0, =0x17741e0	; via 0x3495bc
@@ -1483,6 +1762,7 @@
   3a14f6:	3901		sub	r1, #1
   3a14f8:	2900		cmp	r1, #0
   3a14fa:	d1f9		bne	0x3a14f0
+; "First bat.voltage (mv):" trace
   3a14fc:	48a9		ldr	r0, =0xa0020	; via 0x3a17a4
   3a14fe:	9000		str	r0, [sp, #0]
   3a1500:	a090		add	r0, pc, #576	; 0x240
@@ -1490,6 +1770,7 @@
   3a1504:	1c22		add	r2, r4, #0
   3a1506:	2305		mov	r3, #5
   3a1508:	f039 fb94	bl	0x3dac34
+; "BatOperationMode =" trace
   3a150c:	48a8		ldr	r0, =0x1774cd4	; via 0x3a17b0
   3a150e:	6802		ldr	r2, [r0, #0]
   3a1510:	48a4		ldr	r0, =0xa0020	; via 0x3a17a4
@@ -3207,6 +3488,10 @@
 
 0x17741e0:	abb_sem
 
+0x1774b7c:	16-bit var battery voltage in mV
+
+0x1774cd4:	32-bit var BatOperationMode
+
 0x1774e38:	SPI_GBL_INFO_PTR
 0x1774e3c:	spi_error_ft