FreeCalypso > hg > fc-tourmaline
view src/cs/layer1/include/l1_varex.h @ 268:f2e52cab0a73
abb_inth.c: check all interrupt causes, not just one
The original code used if - else if - else if etc constructs, thus
the first detected interrupt was the only one handled. However,
Iota ITSTATREG is a clear-on-read register, thus if we only handle
the first detected interrupt and skip checking the others, then the
other interrupts will be lost, if more than one interrupt happened
to occur in one ABB interrupt handling cycle - a form of rare race
condition. Change the code to check all interrupts that were read
in this cycle.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sun, 13 Jun 2021 18:17:53 +0000 |
| parents | 4e78acac3d88 |
| children |
line wrap: on
line source
/************* Revision Controle System Header ************* * GSM Layer 1 software * L1_VAREX.H * * Filename l1_varex.h * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ #ifdef L1_ASYNC_C #if (LONG_JUMP == 3) #ifdef __GNUC__ #define SECTION_ATTR __attribute__ ((section (".l1s_global"))) #else #define SECTION_ATTR #pragma DATA_SECTION(l1s,".l1s_global") #pragma DATA_SECTION(l1s_dsp_com,".l1s_global") #pragma DATA_SECTION(l1a_l1s_com,".l1s_global") #pragma DATA_SECTION(l1s_tpu_com,".l1s_global") #pragma DATA_SECTION(l1_config,".l1s_global") #endif #else #define SECTION_ATTR #endif T_L1S_GLOBAL l1s SECTION_ATTR; T_L1A_GLOBAL l1a; T_L1A_L1S_COM l1a_l1s_com SECTION_ATTR; T_L1S_DSP_COM l1s_dsp_com SECTION_ATTR; T_L1S_TPU_COM l1s_tpu_com SECTION_ATTR; #if (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag T_L1_API_HISR l1_apihisr; T_L1A_API_HISR_COM l1a_apihisr_com; #endif // variables for L1 configuration T_L1_CONFIG l1_config SECTION_ATTR; #undef SECTION_ATTR #else // L1_ASYNC_C extern T_L1S_GLOBAL l1s; extern T_L1A_GLOBAL l1a; extern T_L1A_L1S_COM l1a_l1s_com; extern T_L1S_DSP_COM l1s_dsp_com; extern T_L1S_TPU_COM l1s_tpu_com; #if (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag extern T_L1_API_HISR l1_apihisr; extern T_L1A_API_HISR_COM l1a_apihisr_com; #endif // variables for L1 configuration extern T_L1_CONFIG l1_config; #endif extern const UWORD8 ramBootCode[]; // dummy DSP code for boot.
