FreeCalypso > hg > fc-tourmaline
view src/cs/layer1/cfile/l1_small_asm.S @ 275:79cfefc1e2b4
audio mode load: gracefully handle mode files of wrong AEC version
Unfortunately our change of enabling L1_NEW_AEC (which is necessary
in order to bring our Calypso ARM fw into match with the underlying
DSP reality) brings along a change in the audio mode file binary
format and file size - all those new tunable AEC parameters do need
to be stored somewhere, after all. But we already have existing
mode files in the old format, and setting AEC config to garbage when
loading old audio modes (which is what would happen without the
present change) is not an appealing proposition.
The solution implemented in the present change is as follows: the
audio mode loading code checks the file size, and if it differs
from the active version of T_AUDIO_MODE, the T_AUDIO_AEC_CFG structure
is cleared - set to the default (disabled AEC) for the compiled type
of AEC. We got lucky in that this varying T_AUDIO_AEC_CFG structure
sits at the end of T_AUDIO_MODE!
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Fri, 30 Jul 2021 02:55:48 +0000 |
| parents | 4e78acac3d88 |
| children |
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/* * Assembly code extracted out of TI's l1_small.c * * This code is correct ONLY for CHIPSET 10 or 11 as currently used * by FreeCalypso; see TI's original code for what changes would be * needed to support other CHIPSETs. */ .text .code 32 /*-------------------------------------------------------*/ /* _GSM_Small_Sleep */ /* (formerly INT_Small_Sleep) */ /*-------------------------------------------------------*/ /* */ /* Description: small sleep */ /* ------------ */ /* Called by TCT_Schedule main loop of Nucleus */ /*-------------------------------------------------------*/ #define SMALL_SLEEP 0x01 #define ALL_SLEEP 0x04 #define BIG_SMALL_SLEEP 0x05 #define PWR_MNGT 0x01 .globl _GSM_Small_Sleep _GSM_Small_Sleep: ldr r0,Switch ldr r0,[r0] ldrb r1,[r0] cmp r1,#PWR_MNGT bne TCT_Schedule_Loop ldr r0,Mode ldr r0,[r0] ldrb r1,[r0] cmp r1,#SMALL_SLEEP beq Small_sleep_ok cmp r1,#ALL_SLEEP beq Small_sleep_ok cmp r1,#BIG_SMALL_SLEEP bne TCT_Schedule_Loop Small_sleep_ok: // ***************************************************** //reset the DEEP_SLEEP bit 12 of CNTL_ARM_CLK register // (Cf BUG_1278) ldr r0,addrCLKM @ pick up CNTL_ARM_CLK register address ldrh r1,[r0] @ take the current value of the register orr r1,r1,#0x1000 @ reset the bit strh r1,[r0] @ store the result ldr r0,addrCLKM @ pick up CLKM clock register address ldrh r1,[r0] @ take the current value of the register bic r1,r1,#1 @ disable ARM clock strh r1,[r0] B TCT_Schedule_Loop @ Return to TCT_Schedule main loop addrCLKM: .word 0xfffffd00 @ CLKM clock register address Mode: .word mode_authorized Switch: .word switch_PWR_MNGT