comparison src/cs/layer1/cfile/l1_small_asm.S @ 0:4e78acac3d88

src/{condat,cs,gpf,nucleus}: import from Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 16 Oct 2020 06:23:26 +0000
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1 /*
2 * Assembly code extracted out of TI's l1_small.c
3 *
4 * This code is correct ONLY for CHIPSET 10 or 11 as currently used
5 * by FreeCalypso; see TI's original code for what changes would be
6 * needed to support other CHIPSETs.
7 */
8
9 .text
10 .code 32
11
12 /*-------------------------------------------------------*/
13 /* _GSM_Small_Sleep */
14 /* (formerly INT_Small_Sleep) */
15 /*-------------------------------------------------------*/
16 /* */
17 /* Description: small sleep */
18 /* ------------ */
19 /* Called by TCT_Schedule main loop of Nucleus */
20 /*-------------------------------------------------------*/
21
22 #define SMALL_SLEEP 0x01
23 #define ALL_SLEEP 0x04
24 #define BIG_SMALL_SLEEP 0x05
25 #define PWR_MNGT 0x01
26
27 .globl _GSM_Small_Sleep
28 _GSM_Small_Sleep:
29
30 ldr r0,Switch
31 ldr r0,[r0]
32 ldrb r1,[r0]
33 cmp r1,#PWR_MNGT
34 bne TCT_Schedule_Loop
35
36 ldr r0,Mode
37 ldr r0,[r0]
38 ldrb r1,[r0]
39 cmp r1,#SMALL_SLEEP
40 beq Small_sleep_ok
41 cmp r1,#ALL_SLEEP
42 beq Small_sleep_ok
43 cmp r1,#BIG_SMALL_SLEEP
44 bne TCT_Schedule_Loop
45
46 Small_sleep_ok:
47
48 // *****************************************************
49 //reset the DEEP_SLEEP bit 12 of CNTL_ARM_CLK register
50 // (Cf BUG_1278)
51
52 ldr r0,addrCLKM @ pick up CNTL_ARM_CLK register address
53 ldrh r1,[r0] @ take the current value of the register
54 orr r1,r1,#0x1000 @ reset the bit
55 strh r1,[r0] @ store the result
56
57 ldr r0,addrCLKM @ pick up CLKM clock register address
58 ldrh r1,[r0] @ take the current value of the register
59 bic r1,r1,#1 @ disable ARM clock
60 strh r1,[r0]
61
62 B TCT_Schedule_Loop @ Return to TCT_Schedule main loop
63
64 addrCLKM: .word 0xfffffd00 @ CLKM clock register address
65
66 Mode: .word mode_authorized
67 Switch: .word switch_PWR_MNGT