annotate src/cs/drivers/drv_core/abb/abb.c @ 220:0ed36de51973

ABB semaphore protection overhaul The ABB semaphone protection logic that came with TCS211 from TI was broken in several ways: * Some semaphore-protected functions were called from Application_Initialize() context. NU_Obtain_Semaphore() called with NU_SUSPEND fails with NU_INVALID_SUSPEND in this context, but the return value wasn't checked, and NU_Release_Semaphore() would be called unconditionally at the end. The latter call would increment the semaphore count past 1, making the semaphore no longer binary and thus no longer effective for resource protection. The fix is to check the return value from NU_Obtain_Semaphore() and skip the NU_Release_Semaphore() call if the semaphore wasn't properly obtained. * Some SPI hardware manipulation was being done before entering the semaphore- protected critical section. The fix is to reorder the code: first obtain the semaphore, then do everything else. * In the corner case of L1/DSP recovery, l1_abb_power_on() would call some non-semaphore-protected ABB & SPI init functions. The fix is to skip those calls in the case of recovery. * A few additional corner cases existed, all of which are fixed by making ABB semaphore protection 100% consistent for all ABB functions and code paths. There is still one remaining problem of priority inversion: suppose a low- priority task calls an ABB function, and some medium-priority task just happens to preempt right in the middle of that semaphore-protected ABB operation. Then the high-priority SPI task is locked out for a non-deterministic time until that medium-priority task finishes its work and goes back to sleep. This priority inversion problem remains outstanding for now.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 26 Apr 2021 20:55:25 +0000
parents d00662aa64d8
children 160a5b3a076c
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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1 /**********************************************************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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3 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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6 /* product is protected under copyright law and trade secret law as an */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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8 /* rights reserved. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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9 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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10 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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11 /* Filename : abb.c */
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12 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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13 /* Description : Functions to drive the ABB device. */
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14 /* The Serial Port Interface is used to connect the TI */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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15 /* Analog BaseBand (ABB). */
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16 /* It is assumed that the ABB is connected as the SPI */
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17 /* device 0. */
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18 /* */
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19 /* Author : Pascal PUEL */
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20 /* */
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21 /* Version number : 1.3 */
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22 /* */
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23 /* Date and time : 08/22/03 */
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24 /* */
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25 /* Previous delta : Creation */
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26 /* */
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27 /**********************************************************************************/
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28
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29 #include "l1sw.cfg"
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30
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31 #include "chipset.cfg"
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32 #include "board.cfg"
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33 #include "rf.cfg"
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34 #include "swconfig.cfg"
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35 #include "sys.cfg"
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36 #include "abb.h"
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37 #include "l1_macro.h"
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38 #include "l1_confg.h"
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39 #include "clkm/clkm.h" // for wait_ARM_cycles function
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40 #include "abb_inline.h"
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41 #include "ulpd/ulpd.h" // for FRAME_STOP definition
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42 #include "nucleus.h" // for NUCLEUS functions and types
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43 #include "l1_types.h"
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44
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45 #if (OP_L1_STANDALONE == 0)
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46 #include "main/sys_types.h"
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47 #include "rv/general.h"
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48 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function
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49 #else
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50 #include "sys_types.h"
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51 #endif
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52
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53 #if (VCXO_ALGO == 1)
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54 #include "l1_ctl.h"
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55 #endif
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56
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57 #if (RF_FAM == 35)
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58 #include "l1_rf35.h"
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59 #endif
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60
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61 #if (RF_FAM == 12)
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62 #include "tpudrv12.h"
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63 #include "l1_rf12.h"
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64 #endif
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65
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66 #if (RF_FAM == 10)
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67 #include "l1_rf10.h"
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68 #endif
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69
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70 #if (RF_FAM == 8)
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71 #include "l1_rf8.h"
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72 #endif
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73
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74 #if (RF_FAM == 2)
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75 #include "l1_rf2.h"
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76 #endif
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77
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78 /*
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79 * The following conditional compilation control is a FreeCalypso addition.
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80 * TI's original code always configured the BCICONF register with
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81 * MESBB and BBCHGEN bits set, enabling both charging and the measurement
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82 * resistive divider for the backup battery. However, on our primary
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83 * hw targets (Openmoko GTA02 and our own FCDEV3B) Iota's VBACKUP pin
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84 * is unconnected, whereas on Mot C139 and Pirelli DP-L10 "alien" hw
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85 * the VBACKUP situation is unclear. But at least on our known hw
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86 * with VBACKUP unconnected, it is better to leave backup battery charging
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87 * and measurement OFF - TI's original config seems to be a drain on
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88 * the main battery. Therefore, we are going to leave MESBB and BBCHGEN
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89 * off until and unless we have a hw target where backup battery charging
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90 * and measurement are appropriate.
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91 */
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92
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93 #define ENABLE_BACKUP_BATTERY 0
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94
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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95 /*
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96 * The following ABB_sleep_allowed global variable is yet another FreeCalypso
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97 * addition. Here is the issue: some handset boards have the controller/driver
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98 * chip in the LCD powered from Iota VRIO, which is generally a very sensible
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99 * arrangement. As one reference example, our 176x220 pixel TFT LCDs which
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100 * we are considering for our own FC handset draw about 3 mA from their Vci
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101 * supply which we connect to VRIO - perfectly fine when the regulators are
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102 * in their normal Active mode. But what about sleep mode? Sleep mode VRIO
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103 * current limit is only 1 mA, thus the combination of the LCD being on and
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104 * drawing 3 mA with the ABB in sleep mode is invalid. TI's original code
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105 * already had a check for VRPCSTS: PWON and RPWON need to be released and
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106 * the charger needs to be unplugged in order to enter ABB superdeep sleep.
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107 * We are extending this check with one more condition: ABB_sleep_allowed
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108 * needs to be nonzero; the intent is that this variable will be set by the
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109 * code responsible for putting the LCD into its own powerdown mode.
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110 * This logic is included only for affected targets with LCDs.
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111 */
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112
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 #ifdef CONFIG_TARGET_LUNA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 int ABB_sleep_allowed = 0;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
117 #if (ABB_SEMAPHORE_PROTECTION)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 static NU_SEMAPHORE abb_sem;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 /* ABB_Sem_Create() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 /* This function creates the Nucleus semaphore to protect ABB accesses */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 /* against preemption. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 /* No check on the result. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 void ABB_Sem_Create(void)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 {
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
131 // create a semaphore with an initial count of 1 and with FIFO type suspension.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
135 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 /* ABB_Wait_IBIC_Access() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 /* This function waits for the first IBIC access. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 void ABB_Wait_IBIC_Access(void)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 {
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
145 #if (ANLG_FAM == 1)
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
146 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 // (i.e wait 60us + 10% security marge = 66us)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 wait_ARM_cycles(convert_nanosec_to_cycles(66000));
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
149 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
150 // Wait 6 x 32 KHz clock cycles for first IBIC access
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 // (i.e wait 187us + 10% security marge = 210us)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 wait_ARM_cycles(convert_nanosec_to_cycles(210000));
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 /* ABB_Write_Register_on_page() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 /* This function manages all the spi serial transfer to write to an */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 /* ABB register on a specified page. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 /* */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
163 /*-----------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 volatile SYS_UWORD16 status;
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
167 STATUS sem_status;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
169 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 // check if the semaphore has been correctly created and try to obtain it.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
172 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 // as soon as the semaphore is released.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
174
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
175 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
176
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
177 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
179 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
180 SPI_Ready_for_WR
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
181 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
182
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 // set the ABB page for register access
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 ABB_SetPage(page);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 // Write value in reg_id
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 ABB_WriteRegister(reg_id, value);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 // set the ABB page for register access at page 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
192 // Stop the SPI clock
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
193 #ifdef SPI_CLK_LOW_POWER
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
194 SPI_CLK_DISABLE
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
195 #endif
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
196
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
197 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 // release the semaphore only if it has correctly been created.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
199 if(sem_status == NU_SUCCESS)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 NU_Release_Semaphore(&abb_sem);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
203 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 /* ABB_Read_Register_on_page() */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
209 /* */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 /* This function manages all the spi serial transfer to read one */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 /* ABB register on a specified page. */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
212 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
213 /* Returns the real data value of the register. */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
214 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
215 /*-----------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 volatile SYS_UWORD16 status;
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
219 STATUS sem_status;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 SYS_UWORD16 reg_val;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
222 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 // check if the semaphore has been correctly created and try to obtain it.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
225 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 // as soon as the semaphore is released.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
227
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
228 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
229
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
230 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
232 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
233 SPI_Ready_for_RDWR
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
234 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
235
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 /* set the ABB page for register access */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 ABB_SetPage(page);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 /* Read selected ABB register */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 reg_val = ABB_ReadRegister(reg_id);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 /* set the ABB page for register access at page 0 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
245 // Stop the SPI clock
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
246 #ifdef SPI_CLK_LOW_POWER
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
247 SPI_CLK_DISABLE
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
248 #endif
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
249
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
250 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 // release the semaphore only if it has correctly been created.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
252 if(sem_status == NU_SUCCESS)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 NU_Release_Semaphore(&abb_sem);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
256 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 return (reg_val); // Return result
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 /*------------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 /* ABB_free_13M() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 /* */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
264 /* This function sets the 13M clock working in ABB. A wait loop */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 /* is required to allow first slow access to ABB clock register. */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
266 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
267 /* WARNING !! : this function must not be protected by semaphore !! */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
268 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
269 /*------------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 void ABB_free_13M(void)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 volatile SYS_UWORD16 status;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
274 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 SPI_Ready_for_WR
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
276 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 // This transmission frees the CLK13 in ABB.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 ABB_WriteRegister(TOGBR2, 0x08);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 // Wait for first IBIC access
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 ABB_Wait_IBIC_Access();
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 // SW Workaround : This transmission has to be done twice.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 ABB_WriteRegister(TOGBR2, 0x08);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 // Wait for first IBIC access
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 ABB_Wait_IBIC_Access();
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 // Stop the SPI clock
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 #ifdef SPI_CLK_LOW_POWER
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 SPI_CLK_DISABLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 /*------------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 /* ABB_stop_13M() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 /* This function stops the 13M clock in ABB. */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
303 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
304 /*------------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 void ABB_stop_13M(void)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 volatile SYS_UWORD16 status;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
309 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 SPI_Ready_for_WR
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
311 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 // Set ACTIVMCLK = 0.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 ABB_WriteRegister(TOGBR2, 0x04);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 // Wait for first IBIC access
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 ABB_Wait_IBIC_Access();
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 // Stop the SPI clock
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 #ifdef SPI_CLK_LOW_POWER
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 SPI_CLK_DISABLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 /*------------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 /* ABB_Read_Status() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 /* This function reads and returns the value of VRPCSTS ABB register. */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
332 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
333 /*------------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 SYS_UWORD16 ABB_Read_Status(void)
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
335 {
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 volatile SYS_UWORD16 status;
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
337 STATUS sem_status;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 SYS_UWORD16 reg_val;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
340 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 // check if the semaphore has been correctly created and try to obtain it.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
343 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 // as soon as the semaphore is released.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
345
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
346 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
347
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
348 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
350 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
351 SPI_Ready_for_WR
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
352 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
353
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 #if (ANLG_FAM == 1) || (ANLG_FAM == 2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 reg_val = ABB_ReadRegister(VRPCSTS);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359 #elif (ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 reg_val = ABB_ReadRegister(VRPCCFG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
364 // Stop the SPI clock
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
365 #ifdef SPI_CLK_LOW_POWER
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
366 SPI_CLK_DISABLE
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
367 #endif
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
368
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
369 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 // release the semaphore only if it has correctly been created.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
371 if(sem_status == NU_SUCCESS)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 NU_Release_Semaphore(&abb_sem);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
375 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
377 return (reg_val);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 /*------------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 /* ABB_on() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 /* */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
383 /* This function configures ABB registers to work in ON condition */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
384 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
385 /*------------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 volatile SYS_UWORD16 status;
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
389 STATUS sem_status;
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
390 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 SYS_UWORD32 reg;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 #endif
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
393
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
394 #if (ABB_SEMAPHORE_PROTECTION == 3)
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
395
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
396 // check if the semaphore has been correctly created and try to obtain it.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
397 // if the semaphore cannot be obtained, the task is suspended and then resumed
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
398 // as soon as the semaphore is released.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
399
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
400 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
401
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
402 #endif // ABB_SEMAPHORE_PROTECTION
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
403
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
405 if (bRecoveryFlag)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 // RESTITUTE 13MHZ CLOCK TO ABB
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 //---------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 ABB_free_13M();
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 //---------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 ABB_free_13M();
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
416 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 SPI_Ready_for_RDWR
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
418 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 // This transmission disables MADC,AFC,VDL,VUL modules.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
423 ABB_WriteRegister(TOGBR1, 0x0155);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 #if (ANLG_FAM == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 // This transmission disables Band gap fast mode Enable BB charge.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
427 ABB_WriteRegister(VRPCCTL2, 0x1fc);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 /* *********** DC/DC enabling selection ************************************************************** */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 // This transmission changes the register page in OMEGA for usp to pg1.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 SYS_UWORD8 vrpcctrl3_data;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 #if (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 if(modules & DCDC) // check if the DCDC is enabled
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
444 {
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 vrpcctrl3_data |= 0x0002; // set DCDCEN
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
446 }
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
447
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 // This access disables the DCDC.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
449 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data);
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
450 }
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 /* ***************************************************************************************************/
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
455 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 // This transmission enables Omega test register.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
457 ABB_WriteRegister(TAPCTRL, 0x01);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 // This transmission select Omega test instruction.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
460 ABB_WriteRegister(TAPREG, TSPTEST1);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 // This transmission disables Omega test register.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
463 ABB_WriteRegister(TAPCTRL, 0x00);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 /* *************************************************************************************************** */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 // This transmission changes SIM power supply to 3 volts.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
470 ABB_WriteRegister(VRPCCTRL1, 0x45);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 // This transmission enables selected OMEGA modules.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
476 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6);
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
477
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478 if(modules & MADC) // check if the ADC is enabled
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
479 {
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 // This transmission connects the resistive divider to MB and BB.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
481 ABB_WriteRegister(BCICTL1, 0x0005);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
483 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
484 // Restore the ABB checks and debouncing if start on TESTRESETZ
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486 // This transmission changes the register page in the ABB for usp to pg1.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 // This transmission sets the AFCCK to CKIN/2.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
490 ABB_WriteRegister(AFCCTLADD, 0x01);
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
491
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492 // This transmission enables the tapreg.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
493 ABB_WriteRegister(TAPCTRL, 0x01);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 // This transmission enables access to page 2.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
496 ABB_WriteRegister(TAPREG, 0x01b);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 // This transmission changes the register page in the ABB for usp to pg2.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 ABB_SetPage(PAGE2);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 #if (ANLG_FAM == 2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 // Restore push button environment
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 ABB_WriteRegister(0x3C, 0x07);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 #elif (ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 // Restore push button environment
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508 ABB_WriteRegister(0x3C, 0xBF);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 // This transmission enables access to page 0.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 ABB_SetPage(PAGE0);
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
516
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 // reset bit MSKINT1 , if set by TESTRESET
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 reg=ABB_ReadRegister(VRPCSTS) & 0xffe;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 ABB_WriteRegister(VRPCSTS, reg);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522 ABB_SetPage(PAGE2);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 // Restore default for BG behavior in sleep mode
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
525 ABB_WriteRegister(VRPCAUX, 0xBF);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527 // Restore default for deboucing length
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
528 ABB_WriteRegister(VRPCLDO, 0x00F);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
530 // Restore default for INT1 generation, wait time in switch on, checks in switch on
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
531 ABB_WriteRegister(VRPCABBTST, 0x0002);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
532
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
533 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
534
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
535 // This transmission changes the register page in the ABB for usp to pg1.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
536 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
537
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
538 // This transmission sets tapinst to id code.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
539 ABB_WriteRegister(TAPREG, 0x0001);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
540
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
541 // This transmission disables TAPREG access.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
542 ABB_WriteRegister(TAPCTRL, 0x00);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
543
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
544 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
545 // This transmission enables BB charge and BB bridge connection for BB measurements.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
546 #if ENABLE_BACKUP_BATTERY
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
547 ABB_WriteRegister(BCICONF, 0x060);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
548 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
549 ABB_WriteRegister(BCICONF, 0x000);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
550 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
551
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
552 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
553 #if (ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
554 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
555 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
556 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
557 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
558
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
559 /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
560 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
561 /* ****************************************************************************************************/
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
562
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
563 // This transmission enables the tapreg.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
564 ABB_WriteRegister(TAPCTRL, 0x01);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
565
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
566 // This transmission select ABB test instruction.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
567 ABB_WriteRegister(TAPREG, TSPEN);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
568
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
569 // This transmission changes the register page in ABB for usp to pg0.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
570 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
571
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
572 // This transmission enables selected ABB modules.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
573 ABB_WriteRegister(TOGBR1, modules >> 6);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
574
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
575 // enable MB & BB resistive bridges for measurements
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
576 if(modules & MADC) // check if the ADC is enabled
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
577 {
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
578 // This transmission connects the resistive divider to MB and BB.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
579 ABB_WriteRegister(BCICTL1, 0x0001);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
580 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
581
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
582 /********* Sleep definition part ******************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
583 // This transmission changes the register page in the ABB for usp to pg1.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
584 #if (ANLG_FAM == 2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
585 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
586
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
587 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
588 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
589
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
590 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg));
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
591
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
592 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
593 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0;
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
594 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg));
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
595 #elif (ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
596 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
597 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
598 // This transmission changes the register page in the ABB for usp to pg0.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
599 ABB_SetPage(PAGE0);
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
600 #endif
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
601
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
602 // SW workaround for initialization of the audio parts of the ABB to avoid white noise
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
603 // C.f. BUG1941
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
604 // Set VDLR and VULR bits
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
605 // Write TOGBR1 register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
606 // This transmission enables selected ABB modules.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
607 ABB_WriteRegister(TOGBR1, 0x0A);
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
608
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
609 // wait for 1 ms
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
610 wait_ARM_cycles(convert_nanosec_to_cycles(1000000));
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
611
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
612 // Reset VDLS and VULS bits
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
613 // Write TOGBR1 register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
614 // This transmission enables selected ABB modules.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
615 ABB_WriteRegister(TOGBR1, 0x05);
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
616
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
617 // Stop the SPI clock
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
618 #ifdef SPI_CLK_LOW_POWER
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
619 SPI_CLK_DISABLE
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
620 #endif
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
621
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
622 #if (ABB_SEMAPHORE_PROTECTION == 3)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
623 // release the semaphore only if it has correctly been created.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
624 if(sem_status == NU_SUCCESS)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
625 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
626 NU_Release_Semaphore(&abb_sem);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
627 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
628 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
629 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
630
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
631
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
632 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
633 /* ABB_Read_ADC() */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
634 /* */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
635 /* This function manages all the spi serial transfer to read all the */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
636 /* ABB ADC conversion channels. */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
637 /* Stores the result in Buff parameter. */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
638 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
639 /*-----------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
640 void ABB_Read_ADC(SYS_UWORD16 *Buff)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
641 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
642 volatile SYS_UWORD16 status;
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
643 STATUS sem_status;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
644
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
645 #if (ABB_SEMAPHORE_PROTECTION == 3)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
646
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
647 // check if the semaphore has been correctly created and try to obtain it.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
648 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
649 // as soon as the semaphore is released.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
650
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
651 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
652
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
653 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
654
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
655 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
656 SPI_Ready_for_RDWR
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
657 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
658
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
659 // This transmission changes the register page in the ABB for usp to pg0.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
660 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
661
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
662 /* Read all ABB ADC registers */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
663 *Buff++ = ABB_ReadRegister(VBATREG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
664 *Buff++ = ABB_ReadRegister(VCHGREG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
665 *Buff++ = ABB_ReadRegister(ICHGREG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
666 *Buff++ = ABB_ReadRegister(VBKPREG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
667 *Buff++ = ABB_ReadRegister(ADIN1REG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
668 *Buff++ = ABB_ReadRegister(ADIN2REG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
669 *Buff++ = ABB_ReadRegister(ADIN3REG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
670
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
671 #if (ANLG_FAM == 1)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
672 *Buff++ = ABB_ReadRegister(ADIN4XREG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
673 *Buff++ = ABB_ReadRegister(ADIN5YREG);
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
674 #elif (ANLG_FAM == 2)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
675 *Buff++ = ABB_ReadRegister(ADIN4REG);
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
676 #elif (ANLG_FAM == 3)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
677 *Buff++ = ABB_ReadRegister(ADIN4REG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
678 *Buff++ = ABB_ReadRegister(ADIN5REG);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
679 #endif // ANLG_FAM
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
680
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
681 // Stop the SPI clock
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
682 #ifdef SPI_CLK_LOW_POWER
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
683 SPI_CLK_DISABLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
684 #endif
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
685
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
686 #if (ABB_SEMAPHORE_PROTECTION == 3)
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
687 // release the semaphore only if it has correctly been created.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
688 if(sem_status == NU_SUCCESS)
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
689 {
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
690 NU_Release_Semaphore(&abb_sem);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
691 }
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
692 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
693 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
694
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
695
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
696 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
697 /* ABB_Conf_ADC() */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
698 /* */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
699 /* This function manages all the spi serial transfer to: */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
700 /* - select the ABB ADC channels to be converted */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
701 /* - enable/disable EOC interrupt */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
702 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
703 /*-----------------------------------------------------------------------*/
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
704 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
705 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
706 volatile SYS_UWORD16 status;
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
707 STATUS sem_status;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
708 SYS_UWORD16 reg_val;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
709
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
710 #if (ABB_SEMAPHORE_PROTECTION == 3)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
711
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
712 // check if the semaphore has been correctly created and try to obtain it.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
713 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
714 // as soon as the semaphore is released.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
715
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
716 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
717
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
718 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
719
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
720 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
721 SPI_Ready_for_RDWR
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
722 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
723
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
724 // This transmission changes the register page in the ABB for usp to pg0.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
725 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
726
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
727 /* select ADC channels to be converted */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
728 #if (ANLG_FAM == 1)
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
729 ABB_WriteRegister(MADCCTRL1, Channels);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
730 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
731 ABB_WriteRegister(MADCCTRL, Channels);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
732 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
733
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
734 reg_val = ABB_ReadRegister(ITMASK);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
735
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
736 // This transmission configure the End Of Conversion IT without modifying other bits in the same register.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
737 if(ItVal == EOC_INTENA)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
738 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA);
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
739 else if(ItVal == EOC_INTMASK)
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
740 ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
741
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
742 // Stop the SPI clock
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
743 #ifdef SPI_CLK_LOW_POWER
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
744 SPI_CLK_DISABLE
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
745 #endif
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
746
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
747 #if (ABB_SEMAPHORE_PROTECTION == 3)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
748 // release the semaphore only if it has correctly been created.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
749 if(sem_status == NU_SUCCESS)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
750 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
751 NU_Release_Semaphore(&abb_sem);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
752 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
753 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
754 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
755
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
756
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
757 /*------------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
758 /* ABB_sleep() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
759 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
760 /* This function disables the DCDC and returns to PAGE 0. It stops then */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
761 /* the 13MHz clock in ABB. A wait loop s required to allow */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
762 /* first slow access to ABB clock register. */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
763 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
764 /* WARNING !! : this function must not be protected by semaphore !! */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
765 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
766 /* Returns AFC value. */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
767 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
768 /*------------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
769 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
770 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
771 volatile SYS_UWORD16 status;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
772 SYS_UWORD32 afcout_index;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
773 volatile SYS_UWORD16 nb_it;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
774 SYS_UWORD16 reg_val;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
775
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
776 // table for AFC allowed values during Sleep mode. First 5th elements
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
777 // are related to positive AFC values, last 5th to negative ones.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
778 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f};
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
779
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
780 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
781 SPI_Ready_for_RDWR
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
782 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
783
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
784 // COMPUTATION AND PROGRAMMING OF AFC VALUE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
785 //---------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
786 if(afc & 0x1000)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
787 afcout_index = ((afc + 512)>>10) + 1;
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
788 else
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
789 afcout_index = (afc + 512)>>10;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
790
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
791 if (sleep_performed == FRAME_STOP) // Big sleep
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
792 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
793 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
794 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP ////////////////////////////
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
795 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
796
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
797 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
798 else // Deep sleep
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
799 {
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
800 #if(ANLG_FAM == 1)
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
801 // SELECTION OF AFC TEST MODE FOR OMEGA
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
802 //---------------------------------------------------
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
803 // This test configuration allows access on the AFCOUT register
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
804 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
805
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
806 // This transmission enables OMEGA test register.
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
807 ABB_WriteRegister(TAPCTRL, 0x01);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
808
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
809 // This transmission selects OMEGA test instruction.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
810 ABB_WriteRegister(TAPREG, AFCTEST);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
811
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
812 // Set AFCOUT to 0.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
813 ABB_WriteRegister(AFCOUT, 0x00 >> 6);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
814
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
815 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
816
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
817 #elif (ANLG_FAM == 2)
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
818 // This configuration allows access on the AFCOUT register
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
819 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
820
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
821 // Read AFCCTLADD value and enable USP access to AFCOUT register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
822 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
823
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
824 ABB_WriteRegister(AFCCTLADD, reg_val);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
825
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
826 // Set AFCOUT to 0.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
827 ABB_WriteRegister(AFCOUT, 0x00);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
828
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
829 #if ENABLE_BACKUP_BATTERY
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
830 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
831 reg_val = ABB_ReadRegister(BCICONF) & 0x039f;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
832
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
833 ABB_WriteRegister(BCICONF, reg_val);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
834 #endif
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
835
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
836 // Disable the ABB test mode
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
837 ABB_WriteRegister(TAPCTRL, 0x00);
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
838
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
839 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
840
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
841 // Read BCICTL1 value and cut the measurement bridge of MB.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
842 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
843
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
844 ABB_WriteRegister(BCICTL1, reg_val);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
845 #endif
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
846
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
847 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
848 // in Syren during sleep mode. BB charge stays enabled
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
849 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
850 // change the register page in IOTA for usp to pg1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
851
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
852 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
853
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
854 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
855 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
856
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
857 // switch off MADC, AFC, AUXDAC, VOICE.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
858 ABB_WriteRegister(TOGBR1, 0x155);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
859
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
860 // Switch off Analog supply LDO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
861 //-----------------------------
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
862 #if (ANLG_FAM == 1)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
863 ABB_SetPage(PAGE1);
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
864
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
865 // Read VRPCCTL3 register value and switch off VR3.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
866 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
867
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
868 ABB_WriteRegister(VRPCCTRL3, reg_val);
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
869
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
870 #elif (ANLG_FAM == 2)
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
871 // Read VRPCSTS register value and extract status of meaningfull inputs.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
872 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
873
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
874 #ifdef CONFIG_TARGET_LUNA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
875 if (reg_val == 0x30 && ABB_sleep_allowed)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
876 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
877 if (reg_val == 0x30)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
878 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
879 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
880 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
881 ABB_WriteRegister(VRPCDEV, 0x02);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
882 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
883
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
884 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read".
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
885 ABB_WriteRegister(0x0000 | 0x0001, 0x0000);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
886
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
887 #elif (ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
888 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
889 // start the SLPDLY counter in order to switch the ABB in sleep mode
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
890 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
891 // set Syren sleep bit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
892 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
893 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read".
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
894 ABB_WriteRegister(0x0000 | 0x0001, 0x0000);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
895 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
896 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
897
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
898 // Switch to low frequency clock
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
899 ABB_stop_13M();
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
900 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
901
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
902 // Stop the SPI clock
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
903 #ifdef SPI_CLK_LOW_POWER
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
904 SPI_CLK_DISABLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
905 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
906
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
907 #if (OP_L1_STANDALONE == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
908 #if (CHIPSET == 12)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
909 // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
910 // workaround to set APLL_DIV_CLK( internal PU) at high level
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
911 // by default APLL_DIV_CLK is low pulling 80uA on VRIO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
912 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
913 // *(SYS_UWORD16*) (0xFFFEF030)= 0x10;// DPLL mode
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
914 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
915 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
916 return(Afcout_T[afcout_index]);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
917 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
918
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
919
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
920 /*------------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
921 /* ABB_wakeup() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
922 /* */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
923 /* This function sets the 13MHz clock working in ABB. A wait loop */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
924 /* is required to allow first slow access to ABB clock register. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
925 /* Then it re-enables DCDC and returns to PAGE 0. */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
926 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
927 /* WARNING !! : this function must not be protected by semaphore !! */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
928 /* */
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
929 /*------------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
930 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
931 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
932 volatile SYS_UWORD16 status;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
933 SYS_UWORD16 reg_val;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
934
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
935 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
936 SPI_Ready_for_RDWR
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
937 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
938
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
939 if (sleep_performed == FRAME_STOP) // Big sleep
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
940 {
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
941 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
942 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP ////////////////////////////
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
943 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
944 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
945 else // Deep sleep
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
946 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
947 #if (OP_L1_STANDALONE == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
948 #if (CHIPSET == 12)
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
949 // restore context from
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
950 // workaround to set APLL_DIV_CLK( internal PU) at high level
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
951 // by default APLL_DIV_CLK is low pulling 80uA on VRIO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
952 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
953 // *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
954 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
955 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
956
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
957 // Restitutes 13MHZ Clock to ABB
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
958 ABB_free_13M();
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
959
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
960 // Switch ON Analog supply LDO
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
961 #if (ANLG_FAM == 1)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
962 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
963
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
964 // Read VRPCCTL3 register value and switch on VR3.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
965 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
966
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
967 ABB_WriteRegister(VRPCCTRL3, reg_val);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
968 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
969 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
970
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
971 // This transmission switches on MADC, AFC.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
972 ABB_WriteRegister(TOGBR1, 0x280);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
973
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
974 // This transmission sets the AUXAFC2.
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
975 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7));
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
976
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
977 // This transmission sets the AUXAFC1.
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
978 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff));
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
979
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
980 #if (ANLG_FAM == 1)
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
981 // Remove AFC test mode
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
982 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
983
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
984 // This transmission select Omega test instruction.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
985 ABB_WriteRegister(TAPREG, TSPTEST1);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
986
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
987 // Disable test mode selection
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
988 // This transmission disables Omega test register.
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
989 ABB_WriteRegister(TAPCTRL, 0x00 >> 6);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
990
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
991 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
992
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
993 #elif (ANLG_FAM == 2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
994 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
995
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
996 // Read AFCCTLADD register value and disable USP access to AFCOUT register.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
997 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
998
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
999 ABB_WriteRegister(AFCCTLADD, reg_val);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1001 #if ENABLE_BACKUP_BATTERY
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1002 // Read BCICONF register value and enable BB measurement bridge enable BB charge.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1003 reg_val = ABB_ReadRegister(BCICONF) | 0x0060;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1004
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1005 ABB_WriteRegister(BCICONF, reg_val);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1006 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1007
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1008
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1009 /* *************************************************************************************************** */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1010 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1011 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1012 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val));
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1013
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1014 // Enable the ABB test mode
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1015 ABB_WriteRegister(TAPCTRL, 0x01);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1016 ABB_WriteRegister(TAPREG, TSPEN);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1017 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1018
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1019 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1020 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1021
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1022 ABB_WriteRegister(BCICTL1, reg_val);
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1023 #endif
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1024
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1025 #if (ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1026
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1027 ABB_SetPage(PAGE1);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1028
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1029 /* *************************************************************************************************** */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1030 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1031 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1032 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val));
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1033
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1034 /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1035 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1036 /* ****************************************************************************************************/
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1037
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1038 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1039 // This transmission enables IOTA test register
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1040
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1041 ABB_WriteRegister(TAPREG, TSPEN);
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1042 // This transmission select IOTA test instruction
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1043 // This transmission select IOTA test instruction
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1044 /**************************************************************************************************** */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1045
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1046 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1047 #endif
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1048 }
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1049
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1050 // Stop the SPI clock
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1051 #ifdef SPI_CLK_LOW_POWER
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1052 SPI_CLK_DISABLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1053 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1054 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1055
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1056 /*------------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1057 /* ABB_wa_VRPC() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1058 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1059 /* This function initializes the VRPCCTRL1 or VRPCSIM register */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1060 /* according to the ABB used. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1061 /* */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1062 /*------------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1063 void ABB_wa_VRPC(SYS_UWORD16 value)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1064 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1065 volatile SYS_UWORD16 status;
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1066 STATUS sem_status;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1067
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1068 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1069
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1070 // check if the semaphore has been correctly created and try to obtain it.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1071 // if the semaphore cannot be obtained, the task is suspended and then resumed
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1072 // as soon as the semaphore is released.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1073
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1074 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1075
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1076 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1077
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1078 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1079 SPI_Ready_for_WR
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1080 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1081
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1082 ABB_SetPage(PAGE1);
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1083
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1084 #if (ANLG_FAM == 1)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1085 // This transmission initializes the VRPCCTL1 register.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1086 ABB_WriteRegister(VRPCCTRL1, value);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1087
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1088 #elif (ANLG_FAM == 2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1089 // This transmission initializes the VRPCSIM register.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1090 ABB_WriteRegister(VRPCSIM, value);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1091
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1092 #elif (ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1093 // This transmission initializes the VRPCSIMR register.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1094 ABB_WriteRegister(VRPCSIMR, value);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1095
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1096 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1097
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1098 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1099
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1100 // Stop the SPI clock
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1101 #ifdef SPI_CLK_LOW_POWER
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1102 SPI_CLK_DISABLE
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1103 #endif
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1104
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1105 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1106 // release the semaphore only if it has correctly been created.
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1107 if(sem_status == NU_SUCCESS)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1108 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1109 NU_Release_Semaphore(&abb_sem);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1110 }
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1111 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1112 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1113
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1114
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1115 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1116 /* ABB_Write_Uplink_Data() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1117 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1118 /* This function uses the SPI to write to ABB uplink buffer. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1119 /* */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1120 /*-----------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1121 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1122 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1123 SYS_UWORD8 i;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1124 volatile SYS_UWORD16 status;
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1125 STATUS sem_status;
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1126
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1127 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1128
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1129 // check if the semaphore has been correctly created and try to obtain it.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1130 // if the semaphore cannot be obtained, the task is suspended and then resumed
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1131 // as soon as the semaphore is released.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1132
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1133 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1134
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1135 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1136
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1137 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1138 SPI_Ready_for_WR
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1139 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1140
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1141 // Select Page 0 for TOGBR2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1142 ABB_SetPage(PAGE0);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1143
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1144 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1145 ABB_WriteRegister(TOGBR2, 0x10);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1146
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1147 // Clear, assuming that it works like IBUFPTR of Vega
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1148 ABB_WriteRegister(TOGBR2, 0x0);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1149
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1150 // Write the ramp data
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1151 for (i=0;i<16;i++)
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1152 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1153
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1154 // Stop the SPI clock
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1155 #ifdef SPI_CLK_LOW_POWER
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1156 SPI_CLK_DISABLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1157 #endif
220
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1158
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1159 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1160 // release the semaphore only if it has correctly been created.
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1161 if(sem_status == NU_SUCCESS)
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1162 {
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1163 NU_Release_Semaphore(&abb_sem);
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1164 }
0ed36de51973 ABB semaphore protection overhaul
Mychaela Falconia <falcon@freecalypso.org>
parents: 219
diff changeset
1165 #endif // ABB_SEMAPHORE_PROTECTION
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1166 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1167
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1168 //////////////////////// IDEV-INLO integration of sleep mode for Syren ///////////////////////////////////////
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1169
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1170 #if (ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1171
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1172 // Syren Sleep configuration function --------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1173 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1174 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1175 volatile SYS_UWORD16 status,sl_ldo_stat;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1176
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1177 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1178 // change the register page in ABB for usp to pg1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1179
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1180 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1181
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1182 sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1183
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1184 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1185
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1186 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1187 // change the register page in ABB for usp to pg0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1188 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1189 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1190
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1191
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1192 #if (OP_L1_STANDALONE == 0)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1193 /*-----------------------------------------------------------------------*/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1194 /* ABB_Power_Off() */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1195 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1196 /* This function uses the SPI to switch off the ABB. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1197 /* */
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1198 /*-----------------------------------------------------------------------*/
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1199 void ABB_Power_Off(void)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1200 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1201 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks).
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1202 NU_Sleep (30);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1203
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1204 // Wait also until <ON/OFF> key is released.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1205 // This is needed to avoid, if the power key is pressed for a long time, to switch
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1206 // ON-switch OFF the mobile, until the power key is released.
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1207 #if((ANLG_FAM == 1) || (ANLG_FAM == 2))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1208 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) {
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1209 #elif(ANLG_FAM == 3)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1210 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1211 #endif
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1212
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1213 NU_Sleep (1); }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1214
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1215 BZ_KeyBeep_OFF();
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1216
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1217 #if(ANLG_FAM == 1)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1218 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE);
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1219 #elif((ANLG_FAM == 2) || (ANLG_FAM == 3))
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1220 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001);
219
d00662aa64d8 abb.c: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
1221 #endif
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1222 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1223 #endif