view lunakpd1/src/primitives @ 59:d5d14b426faa

lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents c016671a4b4a
children
line wrap: on
line source

header_10pin		numpins 10;
pkg_pushbutton_4pin	numpins 4;