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annotate lunakpd1/src/primitives @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents c016671a4b4a
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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13
c016671a4b4a lunakpd1 project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 header_10pin numpins 10;
c016671a4b4a lunakpd1 project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 pkg_pushbutton_4pin numpins 4;