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comparison lunalcd2/src/vsrc/lcd_module.v @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
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58:99328e0ff61a 59:d5d14b426faa
1 module lcd_module (GND, VCI, IOVCC, DB, RD, WR, RS, CS, RESET, IM0, LEDA, LEDK);
2
3 input GND, VCI, IOVCC;
4 inout [15:0] DB;
5 input RD, WR, RS, CS, RESET, IM0;
6 input LEDA;
7 input [1:3] LEDK;
8
9 /* instantiate the package; the mapping of signals to pins is defined here */
10
11 lcd_module_fp pkg (.pin_1(DB[15]),
12 .pin_2(DB[14]),
13 .pin_3(DB[13]),
14 .pin_4(DB[12]),
15 .pin_5(DB[11]),
16 .pin_6(DB[10]),
17 .pin_7(DB[9]),
18 .pin_8(DB[8]),
19 .pin_9(GND),
20 .pin_10(DB[7]),
21 .pin_11(DB[6]),
22 .pin_12(DB[5]),
23 .pin_13(DB[4]),
24 .pin_14(DB[3]),
25 .pin_15(DB[2]),
26 .pin_16(DB[1]),
27 .pin_17(DB[0]),
28 .pin_18(IOVCC),
29 .pin_19(VCI),
30 .pin_20(RD),
31 .pin_21(WR),
32 .pin_22(RS),
33 .pin_23(CS),
34 .pin_24(RESET),
35 .pin_25(IM0),
36 .pin_26(GND),
37 .pin_27(LEDA),
38 .pin_28(LEDK[1]),
39 .pin_29(LEDK[2]),
40 .pin_30(LEDK[3]),
41 /* the remaining pins are NC */
42 .pin_31(),
43 .pin_32(),
44 .pin_33(),
45 .pin_34(),
46 .pin_35(),
47 .pin_36()
48 );
49
50 endmodule