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annotate lunalcd2/src/vsrc/current_select.v @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
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d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
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1 module current_select (Vio, SET);
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2
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3 input Vio;
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4 output SET;
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5
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6 wire sw_1mA, sw_2mA, sw_4mA, sw_8mA;
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7
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8 pkg_DIP_SW_x4 dipsw ( .pin_1(Vio),
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9 .pin_2(sw_8mA),
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10 .pin_3(Vio),
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11 .pin_4(sw_4mA),
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12 .pin_5(Vio),
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13 .pin_6(sw_2mA),
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14 .pin_7(Vio),
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15 .pin_8(sw_1mA)
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16 );
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17
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18 resistor R_1mA (sw_1mA, SET);
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19 resistor R_2mA (sw_2mA, SET);
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20 resistor R_4mA (sw_4mA, SET);
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21 resistor R_8mA (sw_8mA, SET);
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22
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23 endmodule