FreeCalypso > hg > fc-small-hw
annotate lunalcd2/src/vsrc/lcd_module.v @ 62:907bff95244d
lunalcd2/src/Makefile: generate elements.pcb
| author | Mychaela Falconia <falcon@freecalypso.org> | 
|---|---|
| date | Fri, 25 Jun 2021 19:11:21 +0000 | 
| parents | d5d14b426faa | 
| children | 
| rev | line source | 
|---|---|
| 59 
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lunalcd2: structural Verilog source captured
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changeset | 1 module lcd_module (GND, VCI, IOVCC, DB, RD, WR, RS, CS, RESET, IM0, LEDA, LEDK); | 
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changeset | 2 | 
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changeset | 3 input GND, VCI, IOVCC; | 
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changeset | 4 inout [15:0] DB; | 
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changeset | 5 input RD, WR, RS, CS, RESET, IM0; | 
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changeset | 6 input LEDA; | 
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changeset | 7 input [1:3] LEDK; | 
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changeset | 8 | 
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changeset | 9 /* instantiate the package; the mapping of signals to pins is defined here */ | 
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changeset | 10 | 
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changeset | 11 lcd_module_fp pkg (.pin_1(DB[15]), | 
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changeset | 12 .pin_2(DB[14]), | 
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changeset | 13 .pin_3(DB[13]), | 
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changeset | 14 .pin_4(DB[12]), | 
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changeset | 15 .pin_5(DB[11]), | 
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changeset | 16 .pin_6(DB[10]), | 
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changeset | 17 .pin_7(DB[9]), | 
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changeset | 18 .pin_8(DB[8]), | 
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changeset | 19 .pin_9(GND), | 
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changeset | 20 .pin_10(DB[7]), | 
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changeset | 21 .pin_11(DB[6]), | 
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changeset | 22 .pin_12(DB[5]), | 
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changeset | 23 .pin_13(DB[4]), | 
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changeset | 24 .pin_14(DB[3]), | 
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changeset | 25 .pin_15(DB[2]), | 
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changeset | 26 .pin_16(DB[1]), | 
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changeset | 27 .pin_17(DB[0]), | 
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changeset | 28 .pin_18(IOVCC), | 
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changeset | 29 .pin_19(VCI), | 
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changeset | 30 .pin_20(RD), | 
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changeset | 31 .pin_21(WR), | 
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changeset | 32 .pin_22(RS), | 
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changeset | 33 .pin_23(CS), | 
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changeset | 34 .pin_24(RESET), | 
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changeset | 35 .pin_25(IM0), | 
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changeset | 36 .pin_26(GND), | 
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changeset | 37 .pin_27(LEDA), | 
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changeset | 38 .pin_28(LEDK[1]), | 
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changeset | 39 .pin_29(LEDK[2]), | 
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changeset | 40 .pin_30(LEDK[3]), | 
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changeset | 41 /* the remaining pins are NC */ | 
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changeset | 42 .pin_31(), | 
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changeset | 43 .pin_32(), | 
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changeset | 44 .pin_33(), | 
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changeset | 45 .pin_34(), | 
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changeset | 46 .pin_35(), | 
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changeset | 47 .pin_36() | 
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changeset | 48 ); | 
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changeset | 49 | 
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changeset | 50 endmodule | 
