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annotate sim-fpc-pasv/src/schem.v @ 82:803667312307

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sim-fpc-pasv: schem+BOM design complete
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 25 Oct 2022 06:13:01 +0000
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803667312307 sim-fpc-pasv: schem+BOM design complete
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1 module board ();
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2
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3 wire GND, VCC, VPP, RST, CLK, IO;
803667312307 sim-fpc-pasv: schem+BOM design complete
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4
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5 conn_6pin_plus2 fpc (.pin_1(VCC),
803667312307 sim-fpc-pasv: schem+BOM design complete
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6 .pin_2(RST),
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7 .pin_3(CLK),
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8 .pin_4(IO),
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9 .pin_5(VPP),
803667312307 sim-fpc-pasv: schem+BOM design complete
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10 .pin_6(GND),
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11 /* mounting pads */
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12 .pin_7(GND),
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13 .pin_8(GND)
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14 );
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15
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16 pkg_SIM_socket sim (.pin_1(VCC),
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17 .pin_2(RST),
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18 .pin_3(CLK),
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19 .pin_4(), /* gap in footprint pin numbering */
803667312307 sim-fpc-pasv: schem+BOM design complete
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20 .pin_5(GND),
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21 .pin_6(VPP),
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22 .pin_7(IO),
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23 .pin_8() /* gap in footprint pin numbering */
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24 );
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25
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26 capacitor C1 (VCC, GND);
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27
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28 header_4pin tap_C1_C3 ( .pin_1(GND),
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29 .pin_2(VCC), /* C1 */
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30 .pin_3(RST), /* C2 */
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31 .pin_4(CLK) /* C3 */
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32 );
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33
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34 header_4pin tap_C5_C7 ( .pin_1(GND),
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35 .pin_2(GND), /* C5 */
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36 .pin_3(VPP), /* C6 */
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37 .pin_4(IO) /* C7 */
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38 );
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39
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40 endmodule