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FPGA Makefile: capture yosys stdout
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 01:00:16 +0000
parents beeda5368a77
children 00229623ca81
line wrap: on
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syntax: regexp

\.csv$
\.txt$
\.unet$
\.ps$
\.pdf$

\.asc$
\.bin$
\.json$
\.rpt$

^boards/mv-sniffer/src/elements\.pcb$

^boards/sim-fpc-pasv/pcb/gerbers\.
^boards/sim-fpc-pasv/src/elements\.pcb$