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comparison fpga/sniffer-basic/Makefile @ 9:10c779b8753e

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FPGA Makefile: capture yosys stdout
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 01:00:16 +0000
parents 7cab8e0dd937
children d29dcfa78124
comparison
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8:7cab8e0dd937 9:10c779b8753e
3 PROJ= fpga 3 PROJ= fpga
4 4
5 all: ${PROJ}.bin 5 all: ${PROJ}.bin
6 6
7 ${PROJ}.json: ${VSRC} 7 ${PROJ}.json: ${VSRC}
8 yosys-wrap top $@ ${VSRC} 8 yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
9 9
10 ${PROJ}.asc: ${PROJ}.json ${PCF} 10 ${PROJ}.asc: ${PROJ}.json ${PCF}
11 nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \ 11 nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
12 --json ${PROJ}.json 12 --json ${PROJ}.json
13 13