FreeCalypso > hg > fc-selenite
changeset 173:cb0f52ffd94f
gcc bootentry.S: same MEMIF change as in TMS470 version
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Wed, 19 Jun 2019 05:09:18 +0000 |
| parents | a0f935d68377 |
| children | 097e25b925a2 |
| files | src/cs/system/main/gcc/bootentry.S |
| diffstat | 1 files changed, 10 insertions(+), 0 deletions(-) [+] |
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--- a/src/cs/system/main/gcc/bootentry.S Wed Jun 19 04:38:43 2019 +0000 +++ b/src/cs/system/main/gcc/bootentry.S Wed Jun 19 05:09:18 2019 +0000 @@ -5,6 +5,7 @@ #include "asm_defs.h" #include "fc-target.h" +#include "rf.cfg" #if defined(FLASH) && !defined(CONFIG_TARGET_COMPAL) /* @@ -106,9 +107,18 @@ ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled +@ FreeCalypso change, please see MEMIF-wait-states document +@ in the freecalypso-docs repository for the explanation. + +#if (RF_FAM == 12) +CS0_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable +CS1_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable +CS2_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable +#else CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable +#endif CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable CS4_MEM_REG: .short 0xe85 @ default reset value CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable