FreeCalypso > hg > fc-selenite
diff src/cs/layer1/tpu_drivers/source0/tpudrv12.c @ 153:df9c471ce9e9
l1_rf12.c and tpudrv12.[ch]: updates from Magnetite
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sun, 10 Mar 2019 20:28:06 +0000 |
| parents | b6a5e36de839 |
| children |
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--- a/src/cs/layer1/tpu_drivers/source0/tpudrv12.c Thu Feb 07 00:11:43 2019 +0000 +++ b/src/cs/layer1/tpu_drivers/source0/tpudrv12.c Sun Mar 10 20:28:06 2019 +0000 @@ -779,6 +779,7 @@ TSP_TO_RF(0x0002); *TP_Ptr++ = TPU_MOVE(TSP_ACT, RF_SER_ON); *TP_Ptr++ = TPU_WAIT(1); + /* by happenstance, no change is needed for Pirelli DP-L10 here */ *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET1, 0x21); *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET2, 0x02); *TP_Ptr++ = TPU_MOVE(TSP_CTRL1, TC1_DEVICE_RF | 0x01); @@ -800,7 +801,14 @@ void l1dmacro_RF_wakeup (void) { TP_Ptr = (SYS_UWORD16 *) TPU_RAM; - *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET1, 0x01); + /* + * Change from TI's original code, needed for Pirelli DP-L10: + * configure TSPEN1 (upper nibble of TSP_SPI_SET1) for Rita just like + * the original TSPEN2 config (lower nibble of TSP_SPI_SET2). + * This change does not affect classic TI/OM/FC or Compal platforms + * as they don't use TSPEN1. + */ + *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET1, 0x61); *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET2, 0x06); *TP_Ptr++ = TPU_MOVE(TSP_CTRL1, TC1_DEVICE_RF | 0x01); *TP_Ptr++ = TPU_MOVE(TSP_CTRL2, TC2_WR); @@ -870,7 +878,14 @@ *TP_Ptr++ = TPU_SYNC(0); /* from disassembly, differs from LoCosto version */ - *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET1, 0x20); + /* + * Change from TI's original code, needed for Pirelli DP-L10: + * configure TSPEN1 (upper nibble of TSP_SPI_SET1) for Rita just like + * the original TSPEN2 config (lower nibble of TSP_SPI_SET2). + * This change does not affect classic TI/OM/FC or Compal platforms + * as they don't use TSPEN1. + */ + *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET1, 0x60); *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET2, 0x06); *TP_Ptr++ = TPU_MOVE(TSP_SPI_SET3, 0x00);