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comparison src/cs/system/main/gcc/bootentry.S @ 173:cb0f52ffd94f

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gcc bootentry.S: same MEMIF change as in TMS470 version
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 19 Jun 2019 05:09:18 +0000
parents 7409b22cac61
children
comparison
equal deleted inserted replaced
172:a0f935d68377 173:cb0f52ffd94f
3 * point code that needs to be at the beginning of the flash resides here. 3 * point code that needs to be at the beginning of the flash resides here.
4 */ 4 */
5 5
6 #include "asm_defs.h" 6 #include "asm_defs.h"
7 #include "fc-target.h" 7 #include "fc-target.h"
8 #include "rf.cfg"
8 9
9 #if defined(FLASH) && !defined(CONFIG_TARGET_COMPAL) 10 #if defined(FLASH) && !defined(CONFIG_TARGET_COMPAL)
10 /* 11 /*
11 * Put something sensible in the boot ROM overlay area, just for the 12 * Put something sensible in the boot ROM overlay area, just for the
12 * heck of it, or for extra robustness. 13 * heck of it, or for extra robustness.
104 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state 105 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state
105 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module 106 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module
106 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module 107 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module
107 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled 108 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled
108 109
110 @ FreeCalypso change, please see MEMIF-wait-states document
111 @ in the freecalypso-docs repository for the explanation.
112
113 #if (RF_FAM == 12)
114 CS0_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
115 CS1_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
116 CS2_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
117 #else
109 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable 118 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
110 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable 119 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
111 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable 120 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
121 #endif
112 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable 122 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable
113 CS4_MEM_REG: .short 0xe85 @ default reset value 123 CS4_MEM_REG: .short 0xe85 @ default reset value
114 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable 124 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable
115 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable 125 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
116 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation 126 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation