fc-selenite: src/cs/drivers/drv_core/abb/abb.c annotate

annotate src/cs/drivers/drv_core/abb/abb.c @ 215:ed876f98fdfd

.../drv_core/abb/abb.[ch]: sync with Tourmaline

author	Mychaela Falconia <falcon@freecalypso.org>
date	Mon, 31 Oct 2022 01:20:40 +0000
parents	4f40ae165be4
children

rev	line source
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /**********************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 /* product is protected under copyright law and trade secret law as an */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 /* rights reserved. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 /* Filename : abb.c */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 /* Description : Functions to drive the ABB device. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 /* The Serial Port Interface is used to connect the TI */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 /* Analog BaseBand (ABB). */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16 /* It is assumed that the ABB is connected as the SPI */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 /* device 0. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 /* Author : Pascal PUEL */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21 /* Version number : 1.3 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 /* Date and time : 08/22/03 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 /* Previous delta : Creation */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 /**********************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 #include "l1sw.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 #include "chipset.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 #include "board.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 #include "rf.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 #include "swconfig.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #include "sys.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #include "abb.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #include "l1_macro.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #include "l1_confg.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 #include "clkm/clkm.h" // for wait_ARM_cycles function
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 #include "abb_inline.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 #include "ulpd/ulpd.h" // for FRAME_STOP definition
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 #include "nucleus.h" // for NUCLEUS functions and types
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 #include "l1_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #if (OP_L1_STANDALONE == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #include "main/sys_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #include "rv/general.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #include "sys_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #if (VCXO_ALGO == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #include "l1_ctl.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 #if (RF_FAM == 35)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #include "l1_rf35.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #if (RF_FAM == 12)
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	62 #include "tpudrv12.h"
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #include "l1_rf12.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #if (RF_FAM == 10)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #include "l1_rf10.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 #if (RF_FAM == 8)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #include "l1_rf8.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 #if (RF_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #include "l1_rf2.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 * The following conditional compilation control is a FreeCalypso addition.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 * TI's original code always configured the BCICONF register with
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 * MESBB and BBCHGEN bits set, enabling both charging and the measurement
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82 * resistive divider for the backup battery. However, on our primary
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 * hw targets (Openmoko GTA02 and our own FCDEV3B) Iota's VBACKUP pin
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 * is unconnected, whereas on Mot C139 and Pirelli DP-L10 "alien" hw
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 * the VBACKUP situation is unclear. But at least on our known hw
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 * with VBACKUP unconnected, it is better to leave backup battery charging
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 * and measurement OFF - TI's original config seems to be a drain on
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 * the main battery. Therefore, we are going to leave MESBB and BBCHGEN
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 * off until and unless we have a hw target where backup battery charging
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90 * and measurement are appropriate.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define ENABLE_BACKUP_BATTERY 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94
192 4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	95 /*
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	96 * The following ABB_sleep_allowed global variable is yet another FreeCalypso
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	97 * addition. Here is the issue: some handset boards have the controller/driver
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	98 * chip in the LCD powered from Iota VRIO, which is generally a very sensible
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	99 * arrangement. As one reference example, our 176x220 pixel TFT LCDs which
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	100 * we are considering for our own FC handset draw about 3 mA from their Vci
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	101 * supply which we connect to VRIO - perfectly fine when the regulators are
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	102 * in their normal Active mode. But what about sleep mode? Sleep mode VRIO
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	103 * current limit is only 1 mA, thus the combination of the LCD being on and
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	104 * drawing 3 mA with the ABB in sleep mode is invalid. TI's original code
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	105 * already had a check for VRPCSTS: PWON and RPWON need to be released and
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	106 * the charger needs to be unplugged in order to enter ABB superdeep sleep.
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	107 * We are extending this check with one more condition: ABB_sleep_allowed
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	108 * needs to be nonzero; the intent is that this variable will be set by the
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	109 * code responsible for putting the LCD into its own powerdown mode.
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	110 * This logic is included only for affected targets with LCDs.
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	111 */
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	112
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	113 #ifdef ABB_SLEEP_RESTRICTION
192 4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	114 int ABB_sleep_allowed = 0;
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	115 #endif
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	116
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	117 #if (ABB_SEMAPHORE_PROTECTION)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 static NU_SEMAPHORE abb_sem;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 /* ABB_Sem_Create() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 /* This function creates the Nucleus semaphore to protect ABB accesses */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 /* against preemption. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 /* No check on the result. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 void ABB_Sem_Create(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130 {
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	131 // create a semaphore with an initial count of 1 and with FIFO type suspension.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	135 #endif // ABB_SEMAPHORE_PROTECTION
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 /* ABB_Wait_IBIC_Access() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 /* This function waits for the first IBIC access. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 void ABB_Wait_IBIC_Access(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 {
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	145 #if (ANLG_FAM == 1)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	146 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 // (i.e wait 60us + 10% security marge = 66us)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 wait_ARM_cycles(convert_nanosec_to_cycles(66000));
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	149 #elif ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	150 // Wait 6 x 32 KHz clock cycles for first IBIC access
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 // (i.e wait 187us + 10% security marge = 210us)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 wait_ARM_cycles(convert_nanosec_to_cycles(210000));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 /* ABB_Write_Register_on_page() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 /* This function manages all the spi serial transfer to write to an */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161 /* ABB register on a specified page. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 /* */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	163 /-----------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 volatile SYS_UWORD16 status;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	167 STATUS sem_status;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	169 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 // check if the semaphore has been correctly created and try to obtain it.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	172 // if the semaphore cannot be obtained, the task is suspended and then resumed
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 // as soon as the semaphore is released.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	174
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	175 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	176
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	177 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	178
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	179 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	180 SPI_Ready_for_WR
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	181 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 // set the ABB page for register access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 ABB_SetPage(page);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 // Write value in reg_id
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 ABB_WriteRegister(reg_id, value);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 // set the ABB page for register access at page 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	196
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	197 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	198 // release the semaphore only if it has correctly been created.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	199 if(sem_status == NU_SUCCESS)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	200 {
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	201 NU_Release_Semaphore(&abb_sem);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	202 }
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	203 #endif // ABB_SEMAPHORE_PROTECTION
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 /* ABB_Read_Register_on_page() */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	209 /* */
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210 /* This function manages all the spi serial transfer to read one */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211 /* ABB register on a specified page. */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	212 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	213 /* Returns the real data value of the register. */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	214 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	215 /-----------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 volatile SYS_UWORD16 status;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	219 STATUS sem_status;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	222 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224 // check if the semaphore has been correctly created and try to obtain it.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	225 // if the semaphore cannot be obtained, the task is suspended and then resumed
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 // as soon as the semaphore is released.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	227
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	228 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	229
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	230 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	231
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	232 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	233 SPI_Ready_for_RDWR
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	234 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236 /* set the ABB page for register access */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 ABB_SetPage(page);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239 /* Read selected ABB register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 reg_val = ABB_ReadRegister(reg_id);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 /* set the ABB page for register access at page 0 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	250 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	251 // release the semaphore only if it has correctly been created.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	252 if(sem_status == NU_SUCCESS)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	253 {
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	254 NU_Release_Semaphore(&abb_sem);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	255 }
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	256 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	257
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 return (reg_val); // Return result
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262 /* ABB_free_13M() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 /* */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	264 /* This function sets the 13M clock working in ABB. A wait loop */
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 /* is required to allow first slow access to ABB clock register. */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	266 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	267 /* WARNING !! : this function must not be protected by semaphore !! */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	268 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	269 /------------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 void ABB_free_13M(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	274 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 SPI_Ready_for_WR
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	276 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 // This transmission frees the CLK13 in ABB.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281 ABB_WriteRegister(TOGBR2, 0x08);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 // Wait for first IBIC access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 ABB_Wait_IBIC_Access();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 // SW Workaround : This transmission has to be done twice.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 ABB_WriteRegister(TOGBR2, 0x08);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 // Wait for first IBIC access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 ABB_Wait_IBIC_Access();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 /* ABB_stop_13M() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 /* This function stops the 13M clock in ABB. */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	303 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	304 /------------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 void ABB_stop_13M(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	309 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 SPI_Ready_for_WR
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	311 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 // Set ACTIVMCLK = 0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 ABB_WriteRegister(TOGBR2, 0x04);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318 // Wait for first IBIC access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319 ABB_Wait_IBIC_Access();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 /* ABB_Read_Status() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 /* This function reads and returns the value of VRPCSTS ABB register. */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	332 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	333 /------------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334 SYS_UWORD16 ABB_Read_Status(void)
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	335 {
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336 volatile SYS_UWORD16 status;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	337 STATUS sem_status;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	340 #if ((ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 // check if the semaphore has been correctly created and try to obtain it.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	343 // if the semaphore cannot be obtained, the task is suspended and then resumed
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344 // as soon as the semaphore is released.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	345
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	346 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	347
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	348 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	349
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	350 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	351 SPI_Ready_for_WR
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	352 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #if (ANLG_FAM == 1) \|\| (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 reg_val = ABB_ReadRegister(VRPCSTS);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 reg_val = ABB_ReadRegister(VRPCCFG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	369 #if ((ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	370 // release the semaphore only if it has correctly been created.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	371 if(sem_status == NU_SUCCESS)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	372 {
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	373 NU_Release_Semaphore(&abb_sem);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	374 }
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	375 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	376
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	377 return (reg_val);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 /* ABB_on() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 /* */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	383 /* This function configures ABB registers to work in ON condition */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	384 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	385 /------------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 volatile SYS_UWORD16 status;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	389 STATUS sem_status;
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	390 #if ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 SYS_UWORD32 reg;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	393
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	394 #if (ABB_SEMAPHORE_PROTECTION == 3)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	395
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	396 // check if the semaphore has been correctly created and try to obtain it.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	397 // if the semaphore cannot be obtained, the task is suspended and then resumed
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	398 // as soon as the semaphore is released.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	399
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	400 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	401
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	402 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	403
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	405 if (bRecoveryFlag)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 // RESTITUTE 13MHZ CLOCK TO ABB
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 //---------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409 ABB_free_13M();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412 //---------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 ABB_free_13M();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	416 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417 SPI_Ready_for_RDWR
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	418 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 // This transmission disables MADC,AFC,VDL,VUL modules.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	423 ABB_WriteRegister(TOGBR1, 0x0155);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 #if (ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 // This transmission disables Band gap fast mode Enable BB charge.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	427 ABB_WriteRegister(VRPCCTL2, 0x1fc);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 /* ********* DC/DC enabling selection ************************************************************ */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 // This transmission changes the register page in OMEGA for usp to pg1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 SYS_UWORD8 vrpcctrl3_data;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 #if (CHIPSET == 9) \|\| (CHIPSET == 10) \|\| (CHIPSET == 11)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443 if(modules & DCDC) // check if the DCDC is enabled
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	444 {
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 vrpcctrl3_data \|= 0x0002; // set DCDCEN
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	446 }
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	447
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 // This access disables the DCDC.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	449 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	450 }
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 /* ********************** SELECTION OF TEST MODE FOR ABB ************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 /* ***************************************************************************************************/
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	455 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 // This transmission enables Omega test register.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	457 ABB_WriteRegister(TAPCTRL, 0x01);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 // This transmission select Omega test instruction.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	460 ABB_WriteRegister(TAPREG, TSPTEST1);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462 // This transmission disables Omega test register.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	463 ABB_WriteRegister(TAPCTRL, 0x00);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 /* *************************************************************************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469 // This transmission changes SIM power supply to 3 volts.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	470 ABB_WriteRegister(VRPCCTRL1, 0x45);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 // This transmission enables selected OMEGA modules.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	476 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	477
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478 if(modules & MADC) // check if the ADC is enabled
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	479 {
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 // This transmission connects the resistive divider to MB and BB.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	481 ABB_WriteRegister(BCICTL1, 0x0005);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 }
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	483 #elif ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	484 // Restore the ABB checks and debouncing if start on TESTRESETZ
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 // This transmission changes the register page in the ABB for usp to pg1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 // This transmission sets the AFCCK to CKIN/2.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	490 ABB_WriteRegister(AFCCTLADD, 0x01);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	491
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 // This transmission enables the tapreg.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	493 ABB_WriteRegister(TAPCTRL, 0x01);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495 // This transmission enables access to page 2.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	496 ABB_WriteRegister(TAPREG, 0x01b);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498 // This transmission changes the register page in the ABB for usp to pg2.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 ABB_SetPage(PAGE2);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501 #if (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 // Restore push button environment
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 ABB_WriteRegister(0x3C, 0x07);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507 // Restore push button environment
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508 ABB_WriteRegister(0x3C, 0xBF);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 /* ********************** SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *****************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 // This transmission enables access to page 0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 ABB_SetPage(PAGE0);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	516
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 // reset bit MSKINT1 , if set by TESTRESET
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518 reg=ABB_ReadRegister(VRPCSTS) & 0xffe;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 ABB_WriteRegister(VRPCSTS, reg);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 ABB_SetPage(PAGE2);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 // Restore default for BG behavior in sleep mode
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	525 ABB_WriteRegister(VRPCAUX, 0xBF);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527 // Restore default for deboucing length
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	528 ABB_WriteRegister(VRPCLDO, 0x00F);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 // Restore default for INT1 generation, wait time in switch on, checks in switch on
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	531 ABB_WriteRegister(VRPCABBTST, 0x0002);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 // This transmission changes the register page in the ABB for usp to pg1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 // This transmission sets tapinst to id code.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	539 ABB_WriteRegister(TAPREG, 0x0001);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 // This transmission disables TAPREG access.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	542 ABB_WriteRegister(TAPCTRL, 0x00);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545 // This transmission enables BB charge and BB bridge connection for BB measurements.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546 #if ENABLE_BACKUP_BATTERY
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 ABB_WriteRegister(BCICONF, 0x060);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549 ABB_WriteRegister(BCICONF, 0x000);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552 /* ********************** SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *****************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553 #if (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 /* ********************** SELECTION OF TEST MODE FOR ABB ****************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561 /* ****************************************************************************************************/
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	562
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 // This transmission enables the tapreg.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	564 ABB_WriteRegister(TAPCTRL, 0x01);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 // This transmission select ABB test instruction.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	567 ABB_WriteRegister(TAPREG, TSPEN);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569 // This transmission changes the register page in ABB for usp to pg0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572 // This transmission enables selected ABB modules.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	573 ABB_WriteRegister(TOGBR1, modules >> 6);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	574
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	575 // enable MB & BB resistive bridges for measurements
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	576 if(modules & MADC) // check if the ADC is enabled
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	577 {
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	578 // This transmission connects the resistive divider to MB and BB.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	579 ABB_WriteRegister(BCICTL1, 0x0001);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	580 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	581
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	582 /******* Sleep definition part ****************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	583 // This transmission changes the register page in the ABB for usp to pg1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	584 #if (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	585 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	586
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	587 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	588 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	589
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	590 ABB_WriteRegister(VRPCCFG, (SLPDLY \| reg));
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	591
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	592 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	593 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	594 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE \| reg));
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	595 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	596 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	597 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	598 // This transmission changes the register page in the ABB for usp to pg0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	599 ABB_SetPage(PAGE0);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	600 #endif
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	601
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	602 // SW workaround for initialization of the audio parts of the ABB to avoid white noise
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	603 // C.f. BUG1941
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	604 // Set VDLR and VULR bits
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	605 // Write TOGBR1 register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	606 // This transmission enables selected ABB modules.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	607 ABB_WriteRegister(TOGBR1, 0x0A);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	608
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	609 // wait for 1 ms
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	610 wait_ARM_cycles(convert_nanosec_to_cycles(1000000));
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	611
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	612 // Reset VDLS and VULS bits
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	613 // Write TOGBR1 register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	614 // This transmission enables selected ABB modules.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	615 ABB_WriteRegister(TOGBR1, 0x05);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	616
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	617 // Stop the SPI clock
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	618 #ifdef SPI_CLK_LOW_POWER
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	619 SPI_CLK_DISABLE
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	620 #endif
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	621
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	622 #if (ABB_SEMAPHORE_PROTECTION == 3)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	623 // release the semaphore only if it has correctly been created.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	624 if(sem_status == NU_SUCCESS)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	625 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	626 NU_Release_Semaphore(&abb_sem);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	627 }
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	628 #endif // ABB_SEMAPHORE_PROTECTION
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	629 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	630
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	631
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	632 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	633 /* ABB_Read_ADC() */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	634 /* */
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	635 /* This function manages all the spi serial transfer to read all the */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	636 /* ABB ADC conversion channels. */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	637 /* Stores the result in Buff parameter. */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	638 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	639 /-----------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	640 void ABB_Read_ADC(SYS_UWORD16 *Buff)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	641 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	642 volatile SYS_UWORD16 status;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	643 STATUS sem_status;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	644
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	645 #if (ABB_SEMAPHORE_PROTECTION == 3)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	646
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	647 // check if the semaphore has been correctly created and try to obtain it.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	648 // if the semaphore cannot be obtained, the task is suspended and then resumed
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	649 // as soon as the semaphore is released.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	650
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	651 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	652
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	653 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	654
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	655 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	656 SPI_Ready_for_RDWR
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	657 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	658
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	659 // This transmission changes the register page in the ABB for usp to pg0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	660 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	661
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	662 /* Read all ABB ADC registers */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	663 *Buff++ = ABB_ReadRegister(VBATREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	664 *Buff++ = ABB_ReadRegister(VCHGREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	665 *Buff++ = ABB_ReadRegister(ICHGREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	666 *Buff++ = ABB_ReadRegister(VBKPREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	667 *Buff++ = ABB_ReadRegister(ADIN1REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	668 *Buff++ = ABB_ReadRegister(ADIN2REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	669 *Buff++ = ABB_ReadRegister(ADIN3REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	670
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	671 #if (ANLG_FAM == 1)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	672 *Buff++ = ABB_ReadRegister(ADIN4XREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	673 *Buff++ = ABB_ReadRegister(ADIN5YREG);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	674 #elif (ANLG_FAM == 2)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	675 *Buff++ = ABB_ReadRegister(ADIN4REG);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	676 #elif (ANLG_FAM == 3)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	677 *Buff++ = ABB_ReadRegister(ADIN4REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	678 *Buff++ = ABB_ReadRegister(ADIN5REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	679 #endif // ANLG_FAM
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	680
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	681 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	682 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	683 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	684 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	685
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	686 #if (ABB_SEMAPHORE_PROTECTION == 3)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	687 // release the semaphore only if it has correctly been created.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	688 if(sem_status == NU_SUCCESS)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	689 {
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	690 NU_Release_Semaphore(&abb_sem);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	691 }
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	692 #endif // ABB_SEMAPHORE_PROTECTION
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	693 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	694
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	695
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	696 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	697 /* ABB_Conf_ADC() */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	698 /* */
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	699 /* This function manages all the spi serial transfer to: */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	700 /* - select the ABB ADC channels to be converted */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	701 /* - enable/disable EOC interrupt */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	702 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	703 /-----------------------------------------------------------------------/
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	704 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	705 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	706 volatile SYS_UWORD16 status;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	707 STATUS sem_status;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	708 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	709
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	710 #if (ABB_SEMAPHORE_PROTECTION == 3)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	711
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	712 // check if the semaphore has been correctly created and try to obtain it.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	713 // if the semaphore cannot be obtained, the task is suspended and then resumed
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	714 // as soon as the semaphore is released.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	715
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	716 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	717
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	718 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	719
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	720 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	721 SPI_Ready_for_RDWR
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	722 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	723
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	724 // This transmission changes the register page in the ABB for usp to pg0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	725 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	726
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	727 /* select ADC channels to be converted */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	728 #if (ANLG_FAM == 1)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	729 ABB_WriteRegister(MADCCTRL1, Channels);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	730 #elif ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	731 ABB_WriteRegister(MADCCTRL, Channels);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	732 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	733
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	734 reg_val = ABB_ReadRegister(ITMASK);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	735
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	736 // This transmission configure the End Of Conversion IT without modifying other bits in the same register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	737 if(ItVal == EOC_INTENA)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	738 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	739 else if(ItVal == EOC_INTMASK)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	740 ABB_WriteRegister(ITMASK, reg_val \| EOC_INTMASK);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	741
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	742 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	743 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	744 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	745 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	746
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	747 #if (ABB_SEMAPHORE_PROTECTION == 3)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	748 // release the semaphore only if it has correctly been created.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	749 if(sem_status == NU_SUCCESS)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	750 {
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	751 NU_Release_Semaphore(&abb_sem);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	752 }
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	753 #endif // ABB_SEMAPHORE_PROTECTION
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	754 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	755
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	756
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	757 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	758 /* ABB_sleep() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	759 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	760 /* This function disables the DCDC and returns to PAGE 0. It stops then */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	761 /* the 13MHz clock in ABB. A wait loop s required to allow */
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	762 /* first slow access to ABB clock register. */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	763 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	764 /* WARNING !! : this function must not be protected by semaphore !! */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	765 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	766 /* Returns AFC value. */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	767 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	768 /------------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	769 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	770 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	771 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	772 SYS_UWORD32 afcout_index;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	773 volatile SYS_UWORD16 nb_it;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	774 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	775
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	776 // table for AFC allowed values during Sleep mode. First 5th elements
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	777 // are related to positive AFC values, last 5th to negative ones.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	778 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f};
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	779
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	780 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	781 SPI_Ready_for_RDWR
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	782 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	783
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	784 // COMPUTATION AND PROGRAMMING OF AFC VALUE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	785 //---------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	786 if(afc & 0x1000)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	787 afcout_index = ((afc + 512)>>10) + 1;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	788 else
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	789 afcout_index = (afc + 512)>>10;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	790
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	791 if (sleep_performed == FRAME_STOP) // Big sleep
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	792 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	793 #if ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	794 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP ////////////////////////////
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	795 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	796
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	797 }
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	798 else // Deep sleep
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	799 {
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	800 #if(ANLG_FAM == 1)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	801 // SELECTION OF AFC TEST MODE FOR OMEGA
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	802 //---------------------------------------------------
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	803 // This test configuration allows access on the AFCOUT register
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	804 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	805
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	806 // This transmission enables OMEGA test register.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	807 ABB_WriteRegister(TAPCTRL, 0x01);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	808
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	809 // This transmission selects OMEGA test instruction.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	810 ABB_WriteRegister(TAPREG, AFCTEST);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	811
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	812 // Set AFCOUT to 0.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	813 ABB_WriteRegister(AFCOUT, 0x00 >> 6);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	814
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	815 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	816
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	817 #elif (ANLG_FAM == 2)
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	818 // This configuration allows access on the AFCOUT register
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	819 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	820
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	821 // Read AFCCTLADD value and enable USP access to AFCOUT register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	822 reg_val = (ABB_ReadRegister(AFCCTLADD) \| 0x04);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	823
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	824 ABB_WriteRegister(AFCCTLADD, reg_val);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	825
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	826 // Set AFCOUT to 0.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	827 ABB_WriteRegister(AFCOUT, 0x00);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	828
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	829 #if ENABLE_BACKUP_BATTERY
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	830 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	831 reg_val = ABB_ReadRegister(BCICONF) & 0x039f;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	832
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	833 ABB_WriteRegister(BCICONF, reg_val);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	834 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	835
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	836 // Disable the ABB test mode
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	837 ABB_WriteRegister(TAPCTRL, 0x00);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	838
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	839 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	840
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	841 // Read BCICTL1 value and cut the measurement bridge of MB.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	842 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	843
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	844 ABB_WriteRegister(BCICTL1, reg_val);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	845 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	846
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	847 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	848 // in Syren during sleep mode. BB charge stays enabled
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	849 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	850 // change the register page in IOTA for usp to pg1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	851
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	852 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	853
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	854 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	855 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	856
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	857 // switch off MADC, AFC, AUXDAC, VOICE.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	858 ABB_WriteRegister(TOGBR1, 0x155);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	859
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	860 // Switch off Analog supply LDO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	861 //-----------------------------
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	862 #if (ANLG_FAM == 1)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	863 ABB_SetPage(PAGE1);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	864
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	865 // Read VRPCCTL3 register value and switch off VR3.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	866 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	867
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	868 ABB_WriteRegister(VRPCCTRL3, reg_val);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	869
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	870 #elif (ANLG_FAM == 2)
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	871 // Read VRPCSTS register value and extract status of meaningfull inputs.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	872 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	873
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	874 #ifdef ABB_SLEEP_RESTRICTION
192 4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	875 if (reg_val == 0x30 && ABB_sleep_allowed)
4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	876 #else
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	877 if (reg_val == 0x30)
192 4f40ae165be4 abb.c & init.c: sync with Magnetite for Luna additions Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	878 #endif
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	879 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	880 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	881 ABB_WriteRegister(VRPCDEV, 0x02);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	882 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	883
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	884 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read".
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	885 ABB_WriteRegister(0x0000 \| 0x0001, 0x0000);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	886
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	887 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	888 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	889 // start the SLPDLY counter in order to switch the ABB in sleep mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	890 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	891 // set Syren sleep bit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	892 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	893 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read".
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	894 ABB_WriteRegister(0x0000 \| 0x0001, 0x0000);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	895 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	896 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	897
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	898 // Switch to low frequency clock
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	899 ABB_stop_13M();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	900 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	901
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	902 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	903 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	904 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	905 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	906
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	907 #if (OP_L1_STANDALONE == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	908 #if (CHIPSET == 12)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	909 // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	910 // workaround to set APLL_DIV_CLK( internal PU) at high level
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	911 // by default APLL_DIV_CLK is low pulling 80uA on VRIO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	912 // (SYS_UWORD16) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	913 // (SYS_UWORD16) (0xFFFEF030)= 0x10;// DPLL mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	914 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	915 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	916 return(Afcout_T[afcout_index]);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	917 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	918
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	919
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	920 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	921 /* ABB_wakeup() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	922 /* */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	923 /* This function sets the 13MHz clock working in ABB. A wait loop */
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	924 /* is required to allow first slow access to ABB clock register. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	925 /* Then it re-enables DCDC and returns to PAGE 0. */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	926 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	927 /* WARNING !! : this function must not be protected by semaphore !! */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	928 /* */
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	929 /------------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	930 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	931 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	932 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	933 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	934
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	935 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	936 SPI_Ready_for_RDWR
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	937 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	938
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	939 if (sleep_performed == FRAME_STOP) // Big sleep
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	940 {
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	941 #if ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	942 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP ////////////////////////////
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	943 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	944 }
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	945 else // Deep sleep
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	946 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	947 #if (OP_L1_STANDALONE == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	948 #if (CHIPSET == 12)
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	949 // restore context from
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	950 // workaround to set APLL_DIV_CLK( internal PU) at high level
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	951 // by default APLL_DIV_CLK is low pulling 80uA on VRIO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	952 // (SYS_UWORD16) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	953 // (SYS_UWORD16) (0xFFFEF030)= 0x00;// DPLL mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	954 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	955 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	956
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	957 // Restitutes 13MHZ Clock to ABB
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	958 ABB_free_13M();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	959
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	960 // Switch ON Analog supply LDO
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	961 #if (ANLG_FAM == 1)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	962 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	963
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	964 // Read VRPCCTL3 register value and switch on VR3.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	965 reg_val = ABB_ReadRegister(VRPCCTRL3) \| 0x020;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	966
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	967 ABB_WriteRegister(VRPCCTRL3, reg_val);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	968 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	969 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	970
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	971 // This transmission switches on MADC, AFC.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	972 ABB_WriteRegister(TOGBR1, 0x280);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	973
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	974 // This transmission sets the AUXAFC2.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	975 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7));
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	976
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	977 // This transmission sets the AUXAFC1.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	978 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff));
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	979
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	980 #if (ANLG_FAM == 1)
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	981 // Remove AFC test mode
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	982 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	983
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	984 // This transmission select Omega test instruction.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	985 ABB_WriteRegister(TAPREG, TSPTEST1);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	986
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	987 // Disable test mode selection
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	988 // This transmission disables Omega test register.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	989 ABB_WriteRegister(TAPCTRL, 0x00 >> 6);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	990
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	991 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	992
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	993 #elif (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	994 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	995
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	996 // Read AFCCTLADD register value and disable USP access to AFCOUT register.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	997 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	998
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	999 ABB_WriteRegister(AFCCTLADD, reg_val);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1001 #if ENABLE_BACKUP_BATTERY
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1002 // Read BCICONF register value and enable BB measurement bridge enable BB charge.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1003 reg_val = ABB_ReadRegister(BCICONF) \| 0x0060;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1004
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1005 ABB_WriteRegister(BCICONF, reg_val);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1006 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1007
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1008
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1009 /* *************************************************************************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1010 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1011 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1012 ABB_WriteRegister(VRPCCFG, (SLPDLY \| reg_val));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1013
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1014 // Enable the ABB test mode
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1015 ABB_WriteRegister(TAPCTRL, 0x01);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1016 ABB_WriteRegister(TAPREG, TSPEN);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1017 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1018
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1019 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1020 reg_val = ABB_ReadRegister(BCICTL1) \| 0x0001;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1021
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1022 ABB_WriteRegister(BCICTL1, reg_val);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1023 #endif
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1024
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1025 #if (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1026
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1027 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1028
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1029 /* *************************************************************************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1030 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1031 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1032 ABB_WriteRegister(VRPCCFG, (SLPDLY \| reg_val));
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1033
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1034 /* ********************** SELECTION OF TEST MODE FOR ABB=3 ***************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1035 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1036 /* ****************************************************************************************************/
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1037
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1038 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1039 // This transmission enables IOTA test register
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1040
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1041 ABB_WriteRegister(TAPREG, TSPEN);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1042 // This transmission select IOTA test instruction
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1043 // This transmission select IOTA test instruction
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1044 /**************************************************************************************************** */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1045
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1046 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1047 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1048 }
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1049
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1050 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1051 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1052 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1053 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1054 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1055
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1056 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1057 /* ABB_wa_VRPC() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1058 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1059 /* This function initializes the VRPCCTRL1 or VRPCSIM register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1060 /* according to the ABB used. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1061 /* */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1062 /------------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1063 void ABB_wa_VRPC(SYS_UWORD16 value)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1064 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1065 volatile SYS_UWORD16 status;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1066 STATUS sem_status;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1067
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1068 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1069
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1070 // check if the semaphore has been correctly created and try to obtain it.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1071 // if the semaphore cannot be obtained, the task is suspended and then resumed
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1072 // as soon as the semaphore is released.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1073
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1074 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1075
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1076 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1077
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1078 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1079 SPI_Ready_for_WR
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1080 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1081
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1082 ABB_SetPage(PAGE1);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1083
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1084 #if (ANLG_FAM == 1)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1085 // This transmission initializes the VRPCCTL1 register.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1086 ABB_WriteRegister(VRPCCTRL1, value);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1087
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1088 #elif (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1089 // This transmission initializes the VRPCSIM register.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1090 ABB_WriteRegister(VRPCSIM, value);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1091
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1092 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1093 // This transmission initializes the VRPCSIMR register.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1094 ABB_WriteRegister(VRPCSIMR, value);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1095
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1096 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1097
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1098 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1099
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1100 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1101 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1102 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1103 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1104
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1105 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1106 // release the semaphore only if it has correctly been created.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1107 if(sem_status == NU_SUCCESS)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1108 {
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1109 NU_Release_Semaphore(&abb_sem);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1110 }
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1111 #endif // ABB_SEMAPHORE_PROTECTION
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1112 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1113
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1114
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1115 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1116 /* ABB_Write_Uplink_Data() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1117 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1118 /* This function uses the SPI to write to ABB uplink buffer. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1119 /* */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1120 /-----------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1121 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1122 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1123 SYS_UWORD8 i;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1124 volatile SYS_UWORD16 status;
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1125 STATUS sem_status;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1126
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1127 #if ((ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1128
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1129 // check if the semaphore has been correctly created and try to obtain it.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1130 // if the semaphore cannot be obtained, the task is suspended and then resumed
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1131 // as soon as the semaphore is released.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1132
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1133 sem_status = NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1134
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1135 #endif // ABB_SEMAPHORE_PROTECTION
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1136
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1137 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1138 SPI_Ready_for_WR
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1139 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1140
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1141 // Select Page 0 for TOGBR2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1142 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1143
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1144 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1145 ABB_WriteRegister(TOGBR2, 0x10);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1146
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1147 // Clear, assuming that it works like IBUFPTR of Vega
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1148 ABB_WriteRegister(TOGBR2, 0x0);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1149
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1150 // Write the ramp data
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1151 for (i=0;i<16;i++)
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1152 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6);
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1153
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1154 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1155 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1156 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1157 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1158
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1159 #if ((ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1160 // release the semaphore only if it has correctly been created.
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1161 if(sem_status == NU_SUCCESS)
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1162 {
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1163 NU_Release_Semaphore(&abb_sem);
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1164 }
ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1165 #endif // ABB_SEMAPHORE_PROTECTION
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1166 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1167
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1168 //////////////////////// IDEV-INLO integration of sleep mode for Syren ///////////////////////////////////////
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1169
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1170 #if (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1171
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1172 // Syren Sleep configuration function --------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1173 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1174 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1175 volatile SYS_UWORD16 status,sl_ldo_stat;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1176
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1177 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1178 // change the register page in ABB for usp to pg1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1179
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1180 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1181
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1182 sl_ldo_stat = ((sleep_type<<9\|bg_select<<8) & 0x0374);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1183
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1184 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1185
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1186 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1187 // change the register page in ABB for usp to pg0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1188 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1189 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1190
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1191
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1192 #if (OP_L1_STANDALONE == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1193 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1194 /* ABB_Power_Off() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1195 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1196 /* This function uses the SPI to switch off the ABB. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1197 /* */
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1198 /-----------------------------------------------------------------------/
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1199 void ABB_Power_Off(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1200 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1201 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks).
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1202 NU_Sleep (30);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1203
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1204 // Wait also until <ON/OFF> key is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1205 // This is needed to avoid, if the power key is pressed for a long time, to switch
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1206 // ON-switch OFF the mobile, until the power key is released.
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1207 #if((ANLG_FAM == 1) \|\| (ANLG_FAM == 2))
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1208 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) {
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1209 #elif(ANLG_FAM == 3)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1210 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1211 #endif
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1212
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1213 NU_Sleep (1); }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1214
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1215 BZ_KeyBeep_OFF();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1216
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1217 #if(ANLG_FAM == 1)
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1218 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1219 #elif((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1220 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001);
215 ed876f98fdfd .../drv_core/abb/abb.[ch]: sync with Tourmaline Mychaela Falconia <falcon@freecalypso.org> parents: 192 diff changeset	1221 #endif
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1222 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1223 #endif

FreeCalypso > hg > fc-selenite

annotate src/cs/drivers/drv_core/abb/abb.c @ 215:ed876f98fdfd