FreeCalypso > hg > fc-magnetite
view src/cs/layer1/include/l1_varex.h @ 635:baa0a02bc676
niq32.c DTR handling restored for targets that have it
TI's original TCS211 fw treated GPIO 3 as the DTR input (wired so on C-Sample
and D-Sample boards, also compatible with Leonardo and FCDEV3B which have a
fixed pull-down resistor on this GPIO line), and the code in niq32.c called
UAF_DTRInterruptHandler() (implemented in uartfax.c) from the
IQ_KeypadGPIOHandler() function. But on Openmoko's GTA02 with their official
fw this GPIO is a floating input, all of the DTR handling code in uartfax.c
including the interrupt logic is still there, but the hobbled TCS211-20070608
semi-src delivery which OM got from TI contained a change in niq32.c (which
had been kept in FC until now) that removed the call to
UAF_DTRInterruptHandler() as part of those not-quite-understood "CC test"
hacks.
The present change fixes this bug at a long last: if we are building fw for a
target that has TI's "classic" DTR & DCD GPIO arrangement (dsample, fcmodem and
gtm900), we bring back all of TI's original code in both uartfax.c and niq32.c,
whereas if we are building fw for a target that does not use this classic GPIO
arrangement, the code in niq32.c goes back to what we got from OM and all
DTR & DCD code in uartfax.c is conditioned out. This change also removes the
very last remaining bit of "CC test" bogosity from our FreeCalypso code base.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sun, 19 Jan 2020 01:41:35 +0000 |
| parents | 945cf7f506b2 |
| children |
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/************* Revision Controle System Header ************* * GSM Layer 1 software * L1_VAREX.H * * Filename l1_varex.h * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ #ifdef L1_ASYNC_C #if (LONG_JUMP == 3) #pragma DATA_SECTION(l1s,".l1s_global") #pragma DATA_SECTION(l1s_dsp_com,".l1s_global") #pragma DATA_SECTION(l1a_l1s_com,".l1s_global") #pragma DATA_SECTION(l1s_tpu_com,".l1s_global") #pragma DATA_SECTION(l1_config,".l1s_global") #endif T_L1S_GLOBAL l1s; T_L1A_GLOBAL l1a; T_L1A_L1S_COM l1a_l1s_com; T_L1S_DSP_COM l1s_dsp_com; T_L1S_TPU_COM l1s_tpu_com; #if (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag T_L1_API_HISR l1_apihisr; T_L1A_API_HISR_COM l1a_apihisr_com; #endif // variables for L1 configuration T_L1_CONFIG l1_config; #else // L1_ASYNC_C extern T_L1S_GLOBAL l1s; extern T_L1A_GLOBAL l1a; extern T_L1A_L1S_COM l1a_l1s_com; extern T_L1S_DSP_COM l1s_dsp_com; extern T_L1S_TPU_COM l1s_tpu_com; #if (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag extern T_L1_API_HISR l1_apihisr; extern T_L1A_API_HISR_COM l1a_apihisr_com; #endif // variables for L1 configuration extern T_L1_CONFIG l1_config; #endif extern const UWORD8 ramBootCode[]; // dummy DSP code for boot.