annotate src/cs/layer1/include/l1_varex.h @ 635:baa0a02bc676

niq32.c DTR handling restored for targets that have it TI's original TCS211 fw treated GPIO 3 as the DTR input (wired so on C-Sample and D-Sample boards, also compatible with Leonardo and FCDEV3B which have a fixed pull-down resistor on this GPIO line), and the code in niq32.c called UAF_DTRInterruptHandler() (implemented in uartfax.c) from the IQ_KeypadGPIOHandler() function. But on Openmoko's GTA02 with their official fw this GPIO is a floating input, all of the DTR handling code in uartfax.c including the interrupt logic is still there, but the hobbled TCS211-20070608 semi-src delivery which OM got from TI contained a change in niq32.c (which had been kept in FC until now) that removed the call to UAF_DTRInterruptHandler() as part of those not-quite-understood "CC test" hacks. The present change fixes this bug at a long last: if we are building fw for a target that has TI's "classic" DTR & DCD GPIO arrangement (dsample, fcmodem and gtm900), we bring back all of TI's original code in both uartfax.c and niq32.c, whereas if we are building fw for a target that does not use this classic GPIO arrangement, the code in niq32.c goes back to what we got from OM and all DTR & DCD code in uartfax.c is conditioned out. This change also removes the very last remaining bit of "CC test" bogosity from our FreeCalypso code base.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 19 Jan 2020 01:41:35 +0000
parents 945cf7f506b2
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1_VAREX.H
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4 *
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5 * Filename l1_varex.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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10 #ifdef L1_ASYNC_C
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12 #if (LONG_JUMP == 3)
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13 #pragma DATA_SECTION(l1s,".l1s_global")
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14 #pragma DATA_SECTION(l1s_dsp_com,".l1s_global")
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15 #pragma DATA_SECTION(l1a_l1s_com,".l1s_global")
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16 #pragma DATA_SECTION(l1s_tpu_com,".l1s_global")
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17 #pragma DATA_SECTION(l1_config,".l1s_global")
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18 #endif
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20 T_L1S_GLOBAL l1s;
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21 T_L1A_GLOBAL l1a;
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23 T_L1A_L1S_COM l1a_l1s_com;
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24 T_L1S_DSP_COM l1s_dsp_com;
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25 T_L1S_TPU_COM l1s_tpu_com;
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27 #if (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag
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28 T_L1_API_HISR l1_apihisr;
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29 T_L1A_API_HISR_COM l1a_apihisr_com;
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30 #endif
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31
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32 // variables for L1 configuration
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33 T_L1_CONFIG l1_config;
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35 #else // L1_ASYNC_C
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37 extern T_L1S_GLOBAL l1s;
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38 extern T_L1A_GLOBAL l1a;
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40 extern T_L1A_L1S_COM l1a_l1s_com;
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41 extern T_L1S_DSP_COM l1s_dsp_com;
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42 extern T_L1S_TPU_COM l1s_tpu_com;
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44 #if (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag
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45 extern T_L1_API_HISR l1_apihisr;
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46 extern T_L1A_API_HISR_COM l1a_apihisr_com;
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47 #endif
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48
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49 // variables for L1 configuration
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50 extern T_L1_CONFIG l1_config;
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51 #endif
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54 extern const UWORD8 ramBootCode[]; // dummy DSP code for boot.
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