niq32.c DTR handling restored for targets that have it TI's original TCS211 fw treated GPIO 3 as the DTR input (wired so on C-Sample and D-Sample boards, also compatible with Leonardo and FCDEV3B which have a fixed pull-down resistor on this GPIO line), and the code in niq32.c called UAF_DTRInterruptHandler() (implemented in uartfax.c) from the IQ_KeypadGPIOHandler() function. But on Openmoko's GTA02 with their official fw this GPIO is a floating input, all of the DTR handling code in uartfax.c including the interrupt logic is still there, but the hobbled TCS211-20070608 semi-src delivery which OM got from TI contained a change in niq32.c (which had been kept in FC until now) that removed the call to UAF_DTRInterruptHandler() as part of those not-quite-understood "CC test" hacks. The present change fixes this bug at a long last: if we are building fw for a target that has TI's "classic" DTR & DCD GPIO arrangement (dsample, fcmodem and gtm900), we bring back all of TI's original code in both uartfax.c and niq32.c, whereas if we are building fw for a target that does not use this classic GPIO arrangement, the code in niq32.c goes back to what we got from OM and all DTR & DCD code in uartfax.c is conditioned out. This change also removes the very last remaining bit of "CC test" bogosity from our FreeCalypso code base.

/************* Revision Controle System Header *************
 *                  GSM Layer 1 software
 * L1_DYN_DWL_SIGNA.H
 *
 *        Filename l1_dyn_dwl_signa.h
 *  Copyright 2004 (C) Texas Instruments
 *
 ************* Revision Controle System Header *************/
#if (L1_DYN_DSP_DWNLD == 1)

#ifndef _L1_DYN_DWL_SIGNA_H_
#define _L1_DYN_DWL_SIGNA_H_

#define P_DYN_DWNLD 0x41

// Messages L1S -> L1A
#define L1_DYN_DWNLD_STOP_CON              ( ( P_DYN_DWNLD << 8 ) | 0x02 )

// Messages API HISR -> L1A  //
#define API_L1_DYN_DWNLD_START_CON         ( ( P_DYN_DWNLD << 8 ) | 0x03 )
#define API_L1_DYN_DWNLD_FINISHED          ( ( P_DYN_DWNLD << 8 ) | 0x04 )
#define API_L1_DYN_DWNLD_STOP              ( ( P_DYN_DWNLD << 8 ) | 0x05 )
#define API_L1_CRC_NOT_OK                  ( ( P_DYN_DWNLD << 8 ) | 0x07 )
#define API_L1_CRC_OK                      ( ( P_DYN_DWNLD << 8 ) | 0x08 )
#define API_L1_DYN_DWNLD_UNINST_OK         ( ( P_DYN_DWNLD << 8 ) | 0x09 )

#endif  //_L1_DYN_DWL_SIGNA_H_

#endif  // L1_DYN_DSP_DWNLD