FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/dyn_dwl_include/l1_dyn_dwl_signa.h @ 635:baa0a02bc676
niq32.c DTR handling restored for targets that have it
TI's original TCS211 fw treated GPIO 3 as the DTR input (wired so on C-Sample
and D-Sample boards, also compatible with Leonardo and FCDEV3B which have a
fixed pull-down resistor on this GPIO line), and the code in niq32.c called
UAF_DTRInterruptHandler() (implemented in uartfax.c) from the
IQ_KeypadGPIOHandler() function. But on Openmoko's GTA02 with their official
fw this GPIO is a floating input, all of the DTR handling code in uartfax.c
including the interrupt logic is still there, but the hobbled TCS211-20070608
semi-src delivery which OM got from TI contained a change in niq32.c (which
had been kept in FC until now) that removed the call to
UAF_DTRInterruptHandler() as part of those not-quite-understood "CC test"
hacks.
The present change fixes this bug at a long last: if we are building fw for a
target that has TI's "classic" DTR & DCD GPIO arrangement (dsample, fcmodem and
gtm900), we bring back all of TI's original code in both uartfax.c and niq32.c,
whereas if we are building fw for a target that does not use this classic GPIO
arrangement, the code in niq32.c goes back to what we got from OM and all
DTR & DCD code in uartfax.c is conditioned out. This change also removes the
very last remaining bit of "CC test" bogosity from our FreeCalypso code base.
| author | Mychaela Falconia <falcon@freecalypso.org> |
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| date | Sun, 19 Jan 2020 01:41:35 +0000 |
| parents | 945cf7f506b2 |
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| rev | line source |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1_DYN_DWL_SIGNA.H |
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4 * |
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5 * Filename l1_dyn_dwl_signa.h |
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6 * Copyright 2004 (C) Texas Instruments |
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7 * |
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Mychaela Falconia <falcon@freecalypso.org>
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8 ************* Revision Controle System Header *************/ |
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9 #if (L1_DYN_DSP_DWNLD == 1) |
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10 |
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11 #ifndef _L1_DYN_DWL_SIGNA_H_ |
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12 #define _L1_DYN_DWL_SIGNA_H_ |
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13 |
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14 #define P_DYN_DWNLD 0x41 |
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16 // Messages L1S -> L1A |
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17 #define L1_DYN_DWNLD_STOP_CON ( ( P_DYN_DWNLD << 8 ) | 0x02 ) |
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19 // Messages API HISR -> L1A // |
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20 #define API_L1_DYN_DWNLD_START_CON ( ( P_DYN_DWNLD << 8 ) | 0x03 ) |
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21 #define API_L1_DYN_DWNLD_FINISHED ( ( P_DYN_DWNLD << 8 ) | 0x04 ) |
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22 #define API_L1_DYN_DWNLD_STOP ( ( P_DYN_DWNLD << 8 ) | 0x05 ) |
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23 #define API_L1_CRC_NOT_OK ( ( P_DYN_DWNLD << 8 ) | 0x07 ) |
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24 #define API_L1_CRC_OK ( ( P_DYN_DWNLD << 8 ) | 0x08 ) |
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25 #define API_L1_DYN_DWNLD_UNINST_OK ( ( P_DYN_DWNLD << 8 ) | 0x09 ) |
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27 #endif //_L1_DYN_DWL_SIGNA_H_ |
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29 #endif // L1_DYN_DSP_DWNLD |
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