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view targets/fcdev3b.conf @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 69ffd7f2346d
children 5f00e9afd5d9
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LINK_SCRIPT_SRC=src/cs/system/template/gsm_ds_pirelli_flash.template
RAM_LINK_SCRIPT_SRC=src/cs/system/template/gsm_ds_pirelli_ram.template
MAIN_blob=blobs/patches/main-fchw.lib
INIT_blob=blobs/patches/main-fchw/init.obj
TPUDRV_blob=blobs/libs/tpudrv.lib
FLASH_BASE_ADDR=0
FLASH_SECTOR_SIZE=0x40000