FreeCalypso > hg > fc-magnetite

annotate targets/fcdev3b.conf @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 69ffd7f2346d
children 5f00e9afd5d9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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103
76d139c7a25e targets/fcdev3b.conf: we'll have the same memory IC as the Pirelli,
Mychaela Falconia <falcon@freecalypso.org>
parents: 101
diff changeset
1 LINK_SCRIPT_SRC=src/cs/system/template/gsm_ds_pirelli_flash.template
76d139c7a25e targets/fcdev3b.conf: we'll have the same memory IC as the Pirelli,
Mychaela Falconia <falcon@freecalypso.org>
parents: 101
diff changeset
2 RAM_LINK_SCRIPT_SRC=src/cs/system/template/gsm_ds_pirelli_ram.template
56
e17c1e28389f targets/*.conf: selection of main.lib blob variants
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 MAIN_blob=blobs/patches/main-fchw.lib
101
5c13f9325e2d preparations for rebuilding main.lib from partial source
Mychaela Falconia <falcon@freecalypso.org>
parents: 66
diff changeset
4 INIT_blob=blobs/patches/main-fchw/init.obj
66
0377665aef9d tpudrv.lib blob selection in targets/*.conf
Mychaela Falconia <falcon@freecalypso.org>
parents: 58
diff changeset
5 TPUDRV_blob=blobs/libs/tpudrv.lib
258
13bcc2ed7e44 configure.sh & targets/*.conf: emit FLASH_BASE_ADDR & FLASH_SECTOR_SIZE
Mychaela Falconia <falcon@freecalypso.org>
parents: 103
diff changeset
6 FLASH_BASE_ADDR=0
13bcc2ed7e44 configure.sh & targets/*.conf: emit FLASH_BASE_ADDR & FLASH_SECTOR_SIZE
Mychaela Falconia <falcon@freecalypso.org>
parents: 103
diff changeset
7 FLASH_SECTOR_SIZE=0x40000